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[PULL v2 08/64] target/riscv: add an internals.h header
From: |
Alistair Francis |
Subject: |
[PULL v2 08/64] target/riscv: add an internals.h header |
Date: |
Thu, 2 Jul 2020 09:22:58 -0700 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
The internals.h keeps things that are not relevant to the actual architecture,
only to the implementation, separate.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-6-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/internals.h | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 target/riscv/internals.h
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
new file mode 100644
index 0000000000..22a49af413
--- /dev/null
+++ b/target/riscv/internals.h
@@ -0,0 +1,24 @@
+/*
+ * QEMU RISC-V CPU -- internal functions and types
+ *
+ * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef RISCV_CPU_INTERNALS_H
+#define RISCV_CPU_INTERNALS_H
+
+#include "hw/registerfields.h"
+
+#endif
--
2.27.0
- [PULL v2 00/64] riscv-to-apply queue, Alistair Francis, 2020/07/02
- [PULL v2 02/64] riscv: plic: Add a couple of mising sifive_plic_update calls, Alistair Francis, 2020/07/02
- [PULL v2 01/64] riscv: plic: Honour source priorities, Alistair Francis, 2020/07/02
- [PULL v2 03/64] hw/riscv: Allow 64 bit access to SiFive CLINT, Alistair Francis, 2020/07/02
- [PULL v2 08/64] target/riscv: add an internals.h header,
Alistair Francis <=
- [PULL v2 07/64] target/riscv: add vector configure instruction, Alistair Francis, 2020/07/02
- [PULL v2 05/64] target/riscv: implementation-defined constant parameters, Alistair Francis, 2020/07/02
- [PULL v2 06/64] target/riscv: support vector extension csr, Alistair Francis, 2020/07/02
- [PULL v2 14/64] target/riscv: vector widening integer add and subtract, Alistair Francis, 2020/07/02
- [PULL v2 10/64] target/riscv: add vector index load and store instructions, Alistair Francis, 2020/07/02
- [PULL v2 22/64] target/riscv: vector integer divide instructions, Alistair Francis, 2020/07/02
- [PULL v2 04/64] target/riscv: add vector extension field in CPURISCVState, Alistair Francis, 2020/07/02
- [PULL v2 12/64] target/riscv: add vector amo operations, Alistair Francis, 2020/07/02