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[PULL v2 03/64] hw/riscv: Allow 64 bit access to SiFive CLINT
From: |
Alistair Francis |
Subject: |
[PULL v2 03/64] hw/riscv: Allow 64 bit access to SiFive CLINT |
Date: |
Thu, 2 Jul 2020 09:22:53 -0700 |
Commit 5d971f9e672507210e77d020d89e0e89165c8fc9
"memory: Revert "memory: accept mismatching sizes in
memory_region_access_valid"" broke most RISC-V boards as they do 64 bit
accesses to the CLINT and QEMU would trigger a fault. Fix this failure
by allowing 8 byte accesses.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Message-Id:
<122b78825b077e4dfd39b444d3a46fe894a7804c.1593547870.git.alistair.francis@wdc.com>
---
hw/riscv/sifive_clint.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
index b11ffa0edc..669c21adc2 100644
--- a/hw/riscv/sifive_clint.c
+++ b/hw/riscv/sifive_clint.c
@@ -181,7 +181,7 @@ static const MemoryRegionOps sifive_clint_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
- .max_access_size = 4
+ .max_access_size = 8
}
};
--
2.27.0
- [PULL v2 00/64] riscv-to-apply queue, Alistair Francis, 2020/07/02
- [PULL v2 02/64] riscv: plic: Add a couple of mising sifive_plic_update calls, Alistair Francis, 2020/07/02
- [PULL v2 01/64] riscv: plic: Honour source priorities, Alistair Francis, 2020/07/02
- [PULL v2 03/64] hw/riscv: Allow 64 bit access to SiFive CLINT,
Alistair Francis <=
- [PULL v2 08/64] target/riscv: add an internals.h header, Alistair Francis, 2020/07/02
- [PULL v2 07/64] target/riscv: add vector configure instruction, Alistair Francis, 2020/07/02
- [PULL v2 05/64] target/riscv: implementation-defined constant parameters, Alistair Francis, 2020/07/02
- [PULL v2 06/64] target/riscv: support vector extension csr, Alistair Francis, 2020/07/02
- [PULL v2 14/64] target/riscv: vector widening integer add and subtract, Alistair Francis, 2020/07/02
- [PULL v2 10/64] target/riscv: add vector index load and store instructions, Alistair Francis, 2020/07/02
- [PULL v2 22/64] target/riscv: vector integer divide instructions, Alistair Francis, 2020/07/02
- [PULL v2 04/64] target/riscv: add vector extension field in CPURISCVState, Alistair Francis, 2020/07/02
- [PULL v2 12/64] target/riscv: add vector amo operations, Alistair Francis, 2020/07/02