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[Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs
From: |
Jan Klos |
Subject: |
[Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs |
Date: |
Fri, 15 May 2020 02:41:36 -0000 |
The problem is that disabled cores are not taken into account.. ALL Zen2
CPUs have L3 cache group per CCX and every CCX has 4 cores, the problem
is that some cores in each CCX (1 for 6 and 12-core CPUs, 2 for 3100)
are disabled for some models, but they still use their core ids (as can
be seen in virsh capabilities | grep "cpu id" output in above comments).
Looking at target/i386/cpu.c:5529, this is not taken into account.
Maybe the cleanest way to fix this is to emulate the host topology by
also skipping disabled core ids in the VM? That way, die offset will
actually match the real host CPU topology...
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https://bugs.launchpad.net/bugs/1856335
Title:
Cache Layout wrong on many Zen Arch CPUs
Status in QEMU:
New
Bug description:
AMD CPUs have L3 cache per 2, 3 or 4 cores. Currently, TOPOEXT seems
to always map Cache ass if it was an 4-Core per CCX CPU, which is
incorrect, and costs upwards 30% performance (more realistically 10%)
in L3 Cache Layout aware applications.
Example on a 4-CCX CPU (1950X /w 8 Cores and no SMT):
<cpu mode='custom' match='exact' check='full'>
<model fallback='forbid'>EPYC-IBPB</model>
<vendor>AMD</vendor>
<topology sockets='1' cores='8' threads='1'/>
In windows, coreinfo reports correctly:
****---- Unified Cache 1, Level 3, 8 MB, Assoc 16, LineSize 64
----**** Unified Cache 6, Level 3, 8 MB, Assoc 16, LineSize 64
On a 3-CCX CPU (3960X /w 6 cores and no SMT):
<cpu mode='custom' match='exact' check='full'>
<model fallback='forbid'>EPYC-IBPB</model>
<vendor>AMD</vendor>
<topology sockets='1' cores='6' threads='1'/>
in windows, coreinfo reports incorrectly:
****-- Unified Cache 1, Level 3, 8 MB, Assoc 16, LineSize 64
----** Unified Cache 6, Level 3, 8 MB, Assoc 16, LineSize 64
Validated against 3.0, 3.1, 4.1 and 4.2 versions of qemu-kvm.
With newer Qemu there is a fix (that does behave correctly) in using the dies
parameter:
<qemu:arg value='cores=3,threads=1,dies=2,sockets=1'/>
The problem is that the dies are exposed differently than how AMD does
it natively, they are exposed to Windows as sockets, which means, that
if you are nto a business user, you can't ever have a machine with
more than two CCX (6 cores) as consumer versions of Windows only
supports two sockets. (Should this be reported as a separate bug?)
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- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/03
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/03
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Babu Moger, 2020/05/05
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/07
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Babu Moger, 2020/05/07
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Damir, 2020/05/10
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/10
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Jan Klos, 2020/05/14
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs,
Jan Klos <=
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Jan Klos, 2020/05/15
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Damir, 2020/05/15
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Babu Moger, 2020/05/15
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Jan Klos, 2020/05/17
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Jan Klos, 2020/05/17
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/18
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Babu Moger, 2020/05/18
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/18
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Jan Klos, 2020/05/19
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/19