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[Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs
From: |
Damir |
Subject: |
[Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs |
Date: |
Sun, 10 May 2020 17:47:11 -0000 |
Hello,
I took a look today at the layouts when using 1950X (which previously
worked, and yes, admittedly, I am using Windows / coreinfo), and any
basic config (previously something simple as Sockets=1,Cores=8, Theads=1
(now also Dies=1) worked, but now, the topology presents as if all cores
share L3, and that each two cores share L1C/L1D/L2, like if they were
smt-siblings. I would call this a serious regression.
I don't think using Numa Nodes is an ok way to solve this (especially
not when at least for 4CCX CPUs, this worked flawlessly before), as that
will make numa-aware applications start taking note of numa nodes, and
possibly do wierd things (plus, it introduces more configuration where
it was not needed before).
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https://bugs.launchpad.net/bugs/1856335
Title:
Cache Layout wrong on many Zen Arch CPUs
Status in QEMU:
New
Bug description:
AMD CPUs have L3 cache per 2, 3 or 4 cores. Currently, TOPOEXT seems
to always map Cache ass if it was an 4-Core per CCX CPU, which is
incorrect, and costs upwards 30% performance (more realistically 10%)
in L3 Cache Layout aware applications.
Example on a 4-CCX CPU (1950X /w 8 Cores and no SMT):
<cpu mode='custom' match='exact' check='full'>
<model fallback='forbid'>EPYC-IBPB</model>
<vendor>AMD</vendor>
<topology sockets='1' cores='8' threads='1'/>
In windows, coreinfo reports correctly:
****---- Unified Cache 1, Level 3, 8 MB, Assoc 16, LineSize 64
----**** Unified Cache 6, Level 3, 8 MB, Assoc 16, LineSize 64
On a 3-CCX CPU (3960X /w 6 cores and no SMT):
<cpu mode='custom' match='exact' check='full'>
<model fallback='forbid'>EPYC-IBPB</model>
<vendor>AMD</vendor>
<topology sockets='1' cores='6' threads='1'/>
in windows, coreinfo reports incorrectly:
****-- Unified Cache 1, Level 3, 8 MB, Assoc 16, LineSize 64
----** Unified Cache 6, Level 3, 8 MB, Assoc 16, LineSize 64
Validated against 3.0, 3.1, 4.1 and 4.2 versions of qemu-kvm.
With newer Qemu there is a fix (that does behave correctly) in using the dies
parameter:
<qemu:arg value='cores=3,threads=1,dies=2,sockets=1'/>
The problem is that the dies are exposed differently than how AMD does
it natively, they are exposed to Windows as sockets, which means, that
if you are nto a business user, you can't ever have a machine with
more than two CCX (6 cores) as consumer versions of Windows only
supports two sockets. (Should this be reported as a separate bug?)
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- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/03
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/03
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Babu Moger, 2020/05/05
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/07
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Babu Moger, 2020/05/07
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs,
Damir <=
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/10
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Jan Klos, 2020/05/14
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Jan Klos, 2020/05/14
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Jan Klos, 2020/05/15
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Damir, 2020/05/15
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Babu Moger, 2020/05/15
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Jan Klos, 2020/05/17
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Jan Klos, 2020/05/17
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Heiko Sieger, 2020/05/18
- [Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs, Babu Moger, 2020/05/18