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[PATCH v3 08/16] target/arm: Swap argument order for VSHL during decode
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From: |
Richard Henderson |
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Subject: |
[PATCH v3 08/16] target/arm: Swap argument order for VSHL during decode |
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Date: |
Fri, 8 May 2020 08:21:52 -0700 |
Rather than perform the argument swap during code generation,
perform it during decode. This means it doesn't have to be
special cased later, and we can share code with aarch64 code
generation. Hopefully the decode comment addresses any confusion
that might arise in between.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/neon-dp.decode | 9 +++++++--
target/arm/translate-neon.inc.c | 3 +--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index ec3a92fe75..6b0b6566d6 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -65,8 +65,13 @@ VCGT_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 0
.... @3same
VCGE_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
VCGE_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
-VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same
-VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same
+# The shift operations are of the form Vd = Vm << Vn.
+# By reversing the names of the fields here, we can use standard expanders.
+@3same_rev .... ... . . . size:2 .... .... .... . q:1 . . .... \
+ &3same vn=%vm_dp vm=%vn_dp vd=%vd_dp
+
+VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same_rev
+VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same_rev
VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index aefeff498a..416302bcc7 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -692,8 +692,7 @@ static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
uint32_t rn_ofs, uint32_t rm_ofs, \
uint32_t oprsz, uint32_t maxsz) \
{ \
- /* Note the operation is vshl vd,vm,vn */ \
- tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, \
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, \
oprsz, maxsz, &OPARRAY[vece]); \
} \
DO_3SAME(INSN, gen_##INSN##_3s)
--
2.20.1
- Re: [PATCH v3 02/16] target/arm: Create gen_gvec_{u,s}{rshr,rsra}, (continued)
Re: [PATCH v3 02/16] target/arm: Create gen_gvec_{u,s}{rshr,rsra}, Peter Maydell, 2020/05/12
[PATCH v3 03/16] target/arm: Create gen_gvec_{sri,sli}, Richard Henderson, 2020/05/08
[PATCH v3 04/16] target/arm: Remove unnecessary range check for VSHL, Richard Henderson, 2020/05/08
[PATCH v3 05/16] target/arm: Tidy handle_vec_simd_shri, Richard Henderson, 2020/05/08
[PATCH v3 08/16] target/arm: Swap argument order for VSHL during decode,
Richard Henderson <=
[PATCH v3 07/16] target/arm: Create gen_gvec_{mla,mls}, Richard Henderson, 2020/05/08
[PATCH v3 13/16] target/arm: Pass pointer to qc to qrdmla/qrdmls, Richard Henderson, 2020/05/08
[PATCH v3 14/16] target/arm: Clear tail in gvec_fmul_idx_*, gvec_fmla_idx_*, Richard Henderson, 2020/05/08
[PATCH v3 15/16] target/arm: Vectorize SABD/UABD, Richard Henderson, 2020/05/08
[PATCH v3 10/16] target/arm: Create gen_gvec_{uqadd, sqadd, uqsub, sqsub}, Richard Henderson, 2020/05/08