[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v1 10/15] target/riscv: Fix the interrupt cause code
|
From: |
Alistair Francis |
|
Subject: |
[PATCH v1 10/15] target/riscv: Fix the interrupt cause code |
|
Date: |
Sun, 26 Apr 2020 09:19:39 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 93df7a896d..f7ada23861 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -925,14 +925,15 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
!force_hs_execp) {
+ /* Trap to VS mode */
/*
* See if we need to adjust cause. Yes if its VS mode interrupt
* no if hypervisor has delegated one of hs mode's interrupt
*/
if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
- cause == IRQ_VS_EXT)
+ cause == IRQ_VS_EXT) {
cause = cause - 1;
- /* Trap to VS mode */
+ }
env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
} else if (riscv_cpu_virt_enabled(env)) {
/* Trap into HS mode, from virt */
--
2.26.2
- [PATCH v1 00/15] RISC-V: Update the Hypervisor spec to v0.6, Alistair Francis, 2020/04/26
- [PATCH v1 02/15] target/riscv: Report errors validating 2nd-stage PTEs, Alistair Francis, 2020/04/26
- [PATCH v1 01/15] target/riscv: Set access as data_load when validating stage-2 PTEs, Alistair Francis, 2020/04/26
- [PATCH v1 03/15] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/04/26
- [PATCH v1 04/15] target/riscv: Implement checks for hfence, Alistair Francis, 2020/04/26
- [PATCH v1 05/15] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/04/26
- [PATCH v1 06/15] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/04/26
- [PATCH v1 07/15] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/04/26
- [PATCH v1 08/15] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/04/26
- [PATCH v1 09/15] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/04/26
- [PATCH v1 10/15] target/riscv: Fix the interrupt cause code,
Alistair Francis <=
- [PATCH v1 11/15] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/04/26
- [PATCH v1 12/15] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/04/26
- [PATCH v1 13/15] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/04/26
- [PATCH v1 14/15] target/riscv: Only support little endian guests, Alistair Francis, 2020/04/26