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[PATCH v1 02/15] target/riscv: Report errors validating 2nd-stage PTEs
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From: |
Alistair Francis |
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Subject: |
[PATCH v1 02/15] target/riscv: Report errors validating 2nd-stage PTEs |
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Date: |
Sun, 26 Apr 2020 09:19:16 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_helper.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index ed64190386..0d4a7b752d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -456,8 +456,13 @@ restart:
hwaddr vbase;
/* Do the second stage translation on the base PTE address. */
- get_physical_address(env, &vbase, &vbase_prot, base, MMU_DATA_LOAD,
- mmu_idx, false, true);
+ int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
+ base, MMU_DATA_LOAD,
+ mmu_idx, false, true);
+
+ if (vbase_ret != TRANSLATE_SUCCESS) {
+ return vbase_ret;
+ }
pte_addr = vbase + idx * ptesize;
} else {
--
2.26.2
- [PATCH v1 00/15] RISC-V: Update the Hypervisor spec to v0.6, Alistair Francis, 2020/04/26
- [PATCH v1 02/15] target/riscv: Report errors validating 2nd-stage PTEs,
Alistair Francis <=
- [PATCH v1 01/15] target/riscv: Set access as data_load when validating stage-2 PTEs, Alistair Francis, 2020/04/26
- [PATCH v1 03/15] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/04/26
- [PATCH v1 04/15] target/riscv: Implement checks for hfence, Alistair Francis, 2020/04/26
- [PATCH v1 05/15] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/04/26
- [PATCH v1 06/15] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/04/26
- [PATCH v1 07/15] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/04/26
- [PATCH v1 08/15] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/04/26
- [PATCH v1 09/15] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/04/26
- [PATCH v1 10/15] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/04/26
- [PATCH v1 11/15] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/04/26