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[PATCH v5 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE
From: |
Richard Henderson |
Subject: |
[PATCH v5 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE |
Date: |
Wed, 29 Jan 2020 15:56:09 -0800 |
When VHE is enabled, the exception level below EL2 is not EL1,
but EL0, and so to identify the entry vector offset for exceptions
targeting EL2 we need to look at the width of EL0, not of EL1.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a2eb01f97c..a089ba8a5f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9036,14 +9036,19 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
* immediately lower than the target level is using AArch32 or AArch64
*/
bool is_aa64;
+ uint64_t hcr;
switch (new_el) {
case 3:
is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
break;
case 2:
- is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0;
- break;
+ hcr = arm_hcr_el2_eff(env);
+ if ((hcr & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
+ is_aa64 = (hcr & HCR_RW) != 0;
+ break;
+ }
+ /* fall through */
case 1:
is_aa64 = is_a64(env);
break;
--
2.20.1
- [PATCH v5 21/41] target/arm: Update arm_mmu_idx for VHE, (continued)
- [PATCH v5 21/41] target/arm: Update arm_mmu_idx for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 22/41] target/arm: Update arm_sctlr for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 25/41] target/arm: Add the hypervisor virtual counter, Richard Henderson, 2020/01/29
- [PATCH v5 24/41] target/arm: Update ctr_el0_access for EL2, Richard Henderson, 2020/01/29
- [PATCH v5 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 26/41] target/arm: Update timer access for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime, Richard Henderson, 2020/01/29
- [PATCH v5 31/41] target/arm: Flush tlbs for E2&0 translation regime, Richard Henderson, 2020/01/29
- [PATCH v5 28/41] target/arm: Add VHE system register redirection and aliasing, Richard Henderson, 2020/01/29
- [PATCH v5 29/41] target/arm: Add VHE timer register redirection and aliasing, Richard Henderson, 2020/01/29
- [PATCH v5 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE,
Richard Henderson <=
- [PATCH v5 37/41] target/arm: Enable ARMv8.1-VHE in -cpu max, Richard Henderson, 2020/01/29
- [PATCH v5 32/41] target/arm: Update arm_phys_excp_target_el for TGE, Richard Henderson, 2020/01/29
- [PATCH v5 34/41] target/arm: check TGE and E2H flags for EL0 pauth traps, Richard Henderson, 2020/01/29
- [PATCH v5 33/41] target/arm: Update {fp,sve}_exception_el for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 39/41] target/arm: Pass more cpu state to arm_excp_unmasked, Richard Henderson, 2020/01/29
- [PATCH v5 38/41] target/arm: Move arm_excp_unmasked to cpu.c, Richard Henderson, 2020/01/29
- [PATCH v5 40/41] target/arm: Use bool for unmasked in arm_excp_unmasked, Richard Henderson, 2020/01/29
- [PATCH v5 41/41] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt, Richard Henderson, 2020/01/29
- [PATCH v5 35/41] target/arm: Update get_a64_user_mem_index for VHE, Richard Henderson, 2020/01/29