[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v5 31/41] target/arm: Flush tlbs for E2&0 translation regime
From: |
Richard Henderson |
Subject: |
[PATCH v5 31/41] target/arm: Flush tlbs for E2&0 translation regime |
Date: |
Wed, 29 Jan 2020 15:56:04 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
v5: Flush all EL2 regimes with TLBI ALLE2 (pmm).
---
target/arm/helper.c | 34 +++++++++++++++++++++++++++-------
1 file changed, 27 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 708a2ecf91..9b12ff0ef0 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4174,8 +4174,12 @@ static CPAccessResult aa64_cacheop_access(CPUARMState
*env,
static int vae1_tlbmask(CPUARMState *env)
{
+ /* Since we exclude secure first, we may read HCR_EL2 directly. */
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0;
+ } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE))
+ == (HCR_E2H | HCR_TGE)) {
+ return ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0;
} else {
return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
}
@@ -4219,6 +4223,12 @@ static int alle1_tlbmask(CPUARMState *env)
}
}
+static int alle2_tlbmask(CPUARMState *env)
+{
+ /* TODO: ARMv8.4-SecEL2 */
+ return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E2;
+}
+
static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -4231,10 +4241,10 @@ static void tlbi_aa64_alle1_write(CPUARMState *env,
const ARMCPRegInfo *ri,
static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
+ int mask = alle2_tlbmask(env);
- tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
+ tlb_flush_by_mmuidx(cs, mask);
}
static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4259,8 +4269,9 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,
const ARMCPRegInfo *ri,
uint64_t value)
{
CPUState *cs = env_cpu(env);
+ int mask = alle2_tlbmask(env);
- tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
}
static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4271,6 +4282,15 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env,
const ARMCPRegInfo *ri,
tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3);
}
+static int vae2_tlbmask(CPUARMState *env)
+{
+ if (arm_hcr_el2_eff(env) & HCR_E2H) {
+ return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2;
+ } else {
+ return ARMMMUIdxBit_E2;
+ }
+}
+
static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -4278,11 +4298,11 @@ static void tlbi_aa64_vae2_write(CPUARMState *env,
const ARMCPRegInfo *ri,
* Currently handles both VAE2 and VALE2, since we don't support
* flush-last-level-only.
*/
- ARMCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
+ int mask = vae2_tlbmask(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
+ tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
}
static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
--
2.20.1
- [PATCH v5 23/41] target/arm: Update aa64_zva_access for EL2, (continued)
- [PATCH v5 23/41] target/arm: Update aa64_zva_access for EL2, Richard Henderson, 2020/01/29
- [PATCH v5 21/41] target/arm: Update arm_mmu_idx for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 22/41] target/arm: Update arm_sctlr for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 25/41] target/arm: Add the hypervisor virtual counter, Richard Henderson, 2020/01/29
- [PATCH v5 24/41] target/arm: Update ctr_el0_access for EL2, Richard Henderson, 2020/01/29
- [PATCH v5 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 26/41] target/arm: Update timer access for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime, Richard Henderson, 2020/01/29
- [PATCH v5 31/41] target/arm: Flush tlbs for E2&0 translation regime,
Richard Henderson <=
- [PATCH v5 28/41] target/arm: Add VHE system register redirection and aliasing, Richard Henderson, 2020/01/29
- [PATCH v5 29/41] target/arm: Add VHE timer register redirection and aliasing, Richard Henderson, 2020/01/29
- [PATCH v5 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 37/41] target/arm: Enable ARMv8.1-VHE in -cpu max, Richard Henderson, 2020/01/29
- [PATCH v5 32/41] target/arm: Update arm_phys_excp_target_el for TGE, Richard Henderson, 2020/01/29
- [PATCH v5 34/41] target/arm: check TGE and E2H flags for EL0 pauth traps, Richard Henderson, 2020/01/29
- [PATCH v5 33/41] target/arm: Update {fp,sve}_exception_el for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 39/41] target/arm: Pass more cpu state to arm_excp_unmasked, Richard Henderson, 2020/01/29