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[Qemu-devel] [PATCH 07/13] target/openrisc: Fix lf.ftoi.s
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 07/13] target/openrisc: Fix lf.ftoi.s |
Date: |
Mon, 26 Aug 2019 17:07:39 -0700 |
The specification of this insn is round-to-zero.
Signed-off-by: Richard Henderson <address@hidden>
---
target/openrisc/fpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index b9d2ebbb8c..4cc5b297c5 100644
--- a/target/openrisc/fpu_helper.c
+++ b/target/openrisc/fpu_helper.c
@@ -78,7 +78,7 @@ uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val)
uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val)
{
- return float32_to_int32(val, &env->fp_status);
+ return float32_to_int32_round_to_zero(val, &env->fp_status);
}
#define FLOAT_CALC(name) \
--
2.17.1
- Re: [Qemu-devel] [PATCH 03/13] target/openrisc: Cache R0 in DisasContext, (continued)
- [Qemu-devel] [PATCH 04/13] target/openrisc: Make VR and PPC read-only, Richard Henderson, 2019/08/26
- [Qemu-devel] [PATCH 05/13] target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init, Richard Henderson, 2019/08/26
- [Qemu-devel] [PATCH 02/13] target/openrisc: Replace cpu register array with a function, Richard Henderson, 2019/08/26
- [Qemu-devel] [PATCH 06/13] target/openrisc: Add VR2 and AVR special processor registers, Richard Henderson, 2019/08/26
- [Qemu-devel] [PATCH 07/13] target/openrisc: Fix lf.ftoi.s,
Richard Henderson <=
- [Qemu-devel] [PATCH 08/13] target/openrisc: Check CPUCFG_OF32S for float insns, Richard Henderson, 2019/08/26
- [Qemu-devel] [PATCH 11/13] target/openrisc: Implement move to/from FPCSR, Richard Henderson, 2019/08/26
- [Qemu-devel] [PATCH 12/13] target/openrisc: Implement l.adrp, Richard Henderson, 2019/08/26
- [Qemu-devel] [PATCH 10/13] target/openrisc: Implement unordered fp comparisons, Richard Henderson, 2019/08/26
- [Qemu-devel] [PATCH 09/13] target/openrisc: Add support for ORFPX64A32, Richard Henderson, 2019/08/26