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Re: [Qemu-devel] [PATCH v2 33/68] target/arm: Convert RFE and SRS
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 33/68] target/arm: Convert RFE and SRS |
Date: |
Sun, 25 Aug 2019 16:28:47 +0100 |
On Mon, 19 Aug 2019 at 22:38, Richard Henderson
<address@hidden> wrote:
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target/arm/translate.c | 150 ++++++++++++++---------------------
> target/arm/a32-uncond.decode | 8 ++
> target/arm/t32.decode | 12 +++
> 3 files changed, 81 insertions(+), 89 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index b6d8b7be8c..e268c5168d 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -9980,16 +9980,71 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a)
> return true;
> }
>
> +/*
> + * Unconditional system instructions
> + */
> +
> +static bool trans_RFE(DisasContext *s, arg_RFE *a)
> +{
> + int32_t offset;
> + TCGv_i32 addr, t1, t2;
> +
> + if (IS_USER(s) || !ENABLE_ARCH_6) {
> + return false;
> + }
The legacy thumb decoder for RFE and SRS also has
"not if M profile", which we seem to be missing here ?
> diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode
> index 573ac2cf8e..3b961233e5 100644
> --- a/target/arm/a32-uncond.decode
> +++ b/target/arm/a32-uncond.decode
> @@ -29,3 +29,11 @@
> %imm24h 0:s24 24:1 !function=times_2
>
> BLX_i 1111 101 . ........................ &i imm=%imm24h
> +
> +# System Instructions
> +
> +&rfe rn w pu
> +&srs mode w pu
> +
> +RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe
> +SRS 1111 110 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs
Is this SRS encoding correct? The copy of the Arm ARM I'm looking at
thinks that it starts 1111 100, the same as RFE.
Otherwise
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
- Re: [Qemu-devel] [PATCH v2 28/68] target/arm: Diagnose writeback register in list for LDM for v7, (continued)
- [Qemu-devel] [PATCH v2 26/68] target/arm: Convert MOVW, MOVT, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 27/68] target/arm: Convert LDM, STM, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 32/68] target/arm: Convert SVC, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 24/68] target/arm: Convert Packing, unpacking, saturation, and reversal, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 33/68] target/arm: Convert RFE and SRS, Richard Henderson, 2019/08/19
- Re: [Qemu-devel] [PATCH v2 33/68] target/arm: Convert RFE and SRS,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 31/68] target/arm: Convert B, BL, BLX (immediate), Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 29/68] target/arm: Diagnose too few registers in list for LDM/STM, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 35/68] target/arm: Convert CPS (privileged), Richard Henderson, 2019/08/19