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[Qemu-devel] [PATCH v4 7/7] target/riscv: Use TB_FLAGS_MSTATUS_FS for fl
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v4 7/7] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point |
Date: |
Fri, 23 Aug 2019 08:21:25 -0700 |
Use the TB_FLAGS_MSTATUS_FS macro when enabling floating point in the tb
flags.
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index eb7b5b0af3..0347be453b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -301,7 +301,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env,
target_ulong *pc,
#else
*flags = cpu_mmu_index(env, 0);
if (riscv_cpu_fp_enabled(env)) {
- *flags |= env->mstatus & MSTATUS_FS;
+ *flags |= TB_FLAGS_MSTATUS_FS;
}
#endif
}
--
2.22.0
- [Qemu-devel] [PATCH v4 0/7] RISC-V: Hypervisor prep work part 2, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v4 1/7] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v4 2/7] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v4 3/7] target/riscv: Create function to test if FP is enabled, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v4 4/7] target/riscv: Update the Hypervisor CSRs to v0.4, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v4 5/7] target/riscv: Use both register name and ABI name, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v4 6/7] target/riscv: Fix mstatus dirty mask, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v4 7/7] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point,
Alistair Francis <=