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[Qemu-devel] [PATCH v4 2/7] riscv: plic: Remove unused interrupt functio
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v4 2/7] riscv: plic: Remove unused interrupt functions |
Date: |
Fri, 23 Aug 2019 08:21:12 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Jonathan Behrens <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
---
hw/riscv/sifive_plic.c | 12 ------------
include/hw/riscv/sifive_plic.h | 3 ---
2 files changed, 15 deletions(-)
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index 64a1a10380..98e4304b66 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -162,18 +162,6 @@ static void sifive_plic_update(SiFivePLICState *plic)
}
}
-void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq)
-{
- sifive_plic_set_pending(plic, irq, true);
- sifive_plic_update(plic);
-}
-
-void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq)
-{
- sifive_plic_set_pending(plic, irq, false);
- sifive_plic_update(plic);
-}
-
static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
{
int i, j;
diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h
index b0edba2884..4421e81249 100644
--- a/include/hw/riscv/sifive_plic.h
+++ b/include/hw/riscv/sifive_plic.h
@@ -69,9 +69,6 @@ typedef struct SiFivePLICState {
uint32_t aperture_size;
} SiFivePLICState;
-void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq);
-void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq);
-
DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
uint32_t num_sources, uint32_t num_priorities,
uint32_t priority_base, uint32_t pending_base,
--
2.22.0
- [Qemu-devel] [PATCH v4 0/7] RISC-V: Hypervisor prep work part 2, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v4 1/7] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v4 2/7] riscv: plic: Remove unused interrupt functions,
Alistair Francis <=
- [Qemu-devel] [PATCH v4 3/7] target/riscv: Create function to test if FP is enabled, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v4 4/7] target/riscv: Update the Hypervisor CSRs to v0.4, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v4 5/7] target/riscv: Use both register name and ABI name, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v4 6/7] target/riscv: Fix mstatus dirty mask, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v4 7/7] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point, Alistair Francis, 2019/08/23