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[Qemu-devel] [PATCH v5 25/30] riscv: roms: Update default bios for sifiv
From: |
Bin Meng |
Subject: |
[Qemu-devel] [PATCH v5 25/30] riscv: roms: Update default bios for sifive_u machine |
Date: |
Thu, 22 Aug 2019 22:11:04 -0700 |
With the support of heterogeneous harts and PRCI model, it's now
possible to use the OpenSBI image (PLATFORM=sifive/fu540) built
for the real hardware.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 40968 -> 45064 bytes
roms/Makefile | 4 ++--
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
b/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
index
5d7a1ef6818994bac4a36818ad36043b592ce309..eb22aefdfb468cfe2804cb4b0bc422d8ebcae93b
100644
GIT binary patch
delta 10830
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diff --git a/roms/Makefile b/roms/Makefile
index 775c963..6cf07d3 100644
--- a/roms/Makefile
+++ b/roms/Makefile
@@ -182,8 +182,8 @@ opensbi64-virt:
opensbi64-sifive_u:
$(MAKE) -C opensbi \
CROSS_COMPILE=$(riscv64_cross_prefix) \
- PLATFORM="qemu/sifive_u"
- cp opensbi/build/platform/qemu/sifive_u/firmware/fw_jump.bin
../pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
+ PLATFORM="sifive/fu540"
+ cp opensbi/build/platform/sifive/fu540/firmware/fw_jump.bin
../pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
clean:
rm -rf seabios/.config seabios/out seabios/builds
--
2.7.4
- Re: [Qemu-devel] [PATCH v5 16/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, (continued)
- [Qemu-devel] [PATCH v5 19/30] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 21/30] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 23/30] riscv: sifive_u: Update UART base addresses and IRQs, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 24/30] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 25/30] riscv: roms: Update default bios for sifive_u machine,
Bin Meng <=
- [Qemu-devel] [PATCH v5 30/30] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 28/30] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/23
- Re: [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Alistair Francis, 2019/08/23
- Re: [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Alistair Francis, 2019/08/23
- Message not available