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[Qemu-devel] [RFC PATCH v4 32/75] target/i386: introduce helper-based co
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From: |
Jan Bobek |
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Subject: |
[Qemu-devel] [RFC PATCH v4 32/75] target/i386: introduce helper-based code generator macros |
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Date: |
Wed, 21 Aug 2019 13:29:08 -0400 |
Code generators defined using these macros rely on a helper function
(as emitted by gen_helper_*).
Signed-off-by: Jan Bobek <address@hidden>
---
target/i386/translate.c | 160 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 160 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 603a5b80a1..046914578b 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -5377,6 +5377,166 @@ INSNOP_LDST(xmm, Mhq)
insnop_arg_t(opT3) arg3, insnop_arg_t(opT4) arg4, \
insnop_arg_t(opT5) arg5)
+#define DEF_GEN_INSN0_HELPER(mnem, helper) \
+ GEN_INSN0(mnem) \
+ { \
+ gen_helper_ ## helper(cpu_env); \
+ }
+
+#define DEF_GEN_INSN2_HELPER_EPD(mnem, helper, opT1, opT2) \
+ GEN_INSN2(mnem, opT1, opT2) \
+ { \
+ const TCGv_ptr arg1_ptr = tcg_temp_new_ptr(); \
+ \
+ tcg_gen_addi_ptr(arg1_ptr, cpu_env, arg1); \
+ gen_helper_ ## helper(cpu_env, arg1_ptr, arg2); \
+ \
+ tcg_temp_free_ptr(arg1_ptr); \
+ }
+#define DEF_GEN_INSN2_HELPER_DEP(mnem, helper, opT1, opT2) \
+ GEN_INSN2(mnem, opT1, opT2) \
+ { \
+ const TCGv_ptr arg2_ptr = tcg_temp_new_ptr(); \
+ \
+ tcg_gen_addi_ptr(arg2_ptr, cpu_env, arg2); \
+ gen_helper_ ## helper(arg1, cpu_env, arg2_ptr); \
+ \
+ tcg_temp_free_ptr(arg2_ptr); \
+ }
+#ifdef TARGET_X86_64
+#define DEF_GEN_INSN2_HELPER_EPQ(mnem, helper, opT1, opT2) \
+ DEF_GEN_INSN2_HELPER_EPD(mnem, helper, opT1, opT2)
+#define DEF_GEN_INSN2_HELPER_QEP(mnem, helper, opT1, opT2) \
+ DEF_GEN_INSN2_HELPER_DEP(mnem, helper, opT1, opT2)
+#else /* !TARGET_X86_64 */
+#define DEF_GEN_INSN2_HELPER_EPQ(mnem, helper, opT1, opT2) \
+ GEN_INSN2(mnem, opT1, opT2) \
+ { \
+ g_assert_not_reached(); \
+ }
+#define DEF_GEN_INSN2_HELPER_QEP(mnem, helper, opT1, opT2) \
+ GEN_INSN2(mnem, opT1, opT2) \
+ { \
+ g_assert_not_reached(); \
+ }
+#endif /* !TARGET_X86_64 */
+#define DEF_GEN_INSN2_HELPER_EPP(mnem, helper, opT1, opT2) \
+ GEN_INSN2(mnem, opT1, opT2) \
+ { \
+ const TCGv_ptr arg1_ptr = tcg_temp_new_ptr(); \
+ const TCGv_ptr arg2_ptr = tcg_temp_new_ptr(); \
+ \
+ tcg_gen_addi_ptr(arg1_ptr, cpu_env, arg1); \
+ tcg_gen_addi_ptr(arg2_ptr, cpu_env, arg2); \
+ gen_helper_ ## helper(cpu_env, arg1_ptr, arg2_ptr); \
+ \
+ tcg_temp_free_ptr(arg1_ptr); \
+ tcg_temp_free_ptr(arg2_ptr); \
+ }
+
+#define DEF_GEN_INSN3_HELPER_EPD(mnem, helper, opT1, opT2, opT3) \
+ GEN_INSN3(mnem, opT1, opT2, opT3) \
+ { \
+ const TCGv_ptr arg1_ptr = tcg_temp_new_ptr(); \
+ \
+ assert(arg1 == arg2); \
+ tcg_gen_addi_ptr(arg1_ptr, cpu_env, arg1); \
+ gen_helper_ ## helper(cpu_env, arg1_ptr, arg3); \
+ \
+ tcg_temp_free_ptr(arg1_ptr); \
+ }
+#ifdef TARGET_X86_64
+#define DEF_GEN_INSN3_HELPER_EPQ(mnem, helper, opT1, opT2, opT3) \
+ DEF_GEN_INSN3_HELPER_EPD(mnem, helper, opT1, opT2, opT3)
+#else /* !TARGET_X86_64 */
+#define DEF_GEN_INSN3_HELPER_EPQ(mnem, helper, opT1, opT2, opT3) \
+ GEN_INSN3(mnem, opT1, opT2, opT3) \
+ { \
+ g_assert_not_reached(); \
+ }
+#endif /* !TARGET_X86_64 */
+#define DEF_GEN_INSN3_HELPER_EPP(mnem, helper, opT1, opT2, opT3) \
+ GEN_INSN3(mnem, opT1, opT2, opT3) \
+ { \
+ const TCGv_ptr arg1_ptr = tcg_temp_new_ptr(); \
+ const TCGv_ptr arg3_ptr = tcg_temp_new_ptr(); \
+ \
+ assert(arg1 == arg2); \
+ tcg_gen_addi_ptr(arg1_ptr, cpu_env, arg1); \
+ tcg_gen_addi_ptr(arg3_ptr, cpu_env, arg3); \
+ gen_helper_ ## helper(cpu_env, arg1_ptr, arg3_ptr); \
+ \
+ tcg_temp_free_ptr(arg1_ptr); \
+ tcg_temp_free_ptr(arg3_ptr); \
+ }
+#define DEF_GEN_INSN3_HELPER_PPI(mnem, helper, opT1, opT2, opT3) \
+ GEN_INSN3(mnem, opT1, opT2, opT3) \
+ { \
+ const TCGv_ptr arg1_ptr = tcg_temp_new_ptr(); \
+ const TCGv_ptr arg2_ptr = tcg_temp_new_ptr(); \
+ const TCGv_i32 arg3_r32 = tcg_temp_new_i32(); \
+ \
+ tcg_gen_addi_ptr(arg1_ptr, cpu_env, arg1); \
+ tcg_gen_addi_ptr(arg2_ptr, cpu_env, arg2); \
+ tcg_gen_movi_i32(arg3_r32, arg3); \
+ gen_helper_ ## helper(arg1_ptr, arg2_ptr, arg3_r32); \
+ \
+ tcg_temp_free_ptr(arg1_ptr); \
+ tcg_temp_free_ptr(arg2_ptr); \
+ tcg_temp_free_i32(arg3_r32); \
+ }
+#define DEF_GEN_INSN3_HELPER_EPPI(mnem, helper, opT1, opT2, opT3) \
+ GEN_INSN3(mnem, opT1, opT2, opT3) \
+ { \
+ const TCGv_ptr arg1_ptr = tcg_temp_new_ptr(); \
+ const TCGv_ptr arg2_ptr = tcg_temp_new_ptr(); \
+ const TCGv_i32 arg3_r32 = tcg_temp_new_i32(); \
+ \
+ tcg_gen_addi_ptr(arg1_ptr, cpu_env, arg1); \
+ tcg_gen_addi_ptr(arg2_ptr, cpu_env, arg2); \
+ tcg_gen_movi_i32(arg3_r32, arg3); \
+ gen_helper_ ## helper(cpu_env, arg1_ptr, arg2_ptr, arg3_r32); \
+ \
+ tcg_temp_free_ptr(arg1_ptr); \
+ tcg_temp_free_ptr(arg2_ptr); \
+ tcg_temp_free_i32(arg3_r32); \
+ }
+
+#define DEF_GEN_INSN4_HELPER_PPI(mnem, helper, opT1, opT2, opT3, opT4) \
+ GEN_INSN4(mnem, opT1, opT2, opT3, opT4) \
+ { \
+ const TCGv_ptr arg1_ptr = tcg_temp_new_ptr(); \
+ const TCGv_ptr arg3_ptr = tcg_temp_new_ptr(); \
+ const TCGv_i32 arg4_r32 = tcg_temp_new_i32(); \
+ \
+ assert(arg1 == arg2); \
+ tcg_gen_addi_ptr(arg1_ptr, cpu_env, arg1); \
+ tcg_gen_addi_ptr(arg3_ptr, cpu_env, arg3); \
+ tcg_gen_movi_i32(arg4_r32, arg4); \
+ gen_helper_ ## helper(arg1_ptr, arg3_ptr, arg4_r32); \
+ \
+ tcg_temp_free_ptr(arg1_ptr); \
+ tcg_temp_free_ptr(arg3_ptr); \
+ tcg_temp_free_i32(arg4_r32); \
+ }
+#define DEF_GEN_INSN4_HELPER_EPPI(mnem, helper, opT1, opT2, opT3, opT4) \
+ GEN_INSN4(mnem, opT1, opT2, opT3, opT4) \
+ { \
+ const TCGv_ptr arg1_ptr = tcg_temp_new_ptr(); \
+ const TCGv_ptr arg3_ptr = tcg_temp_new_ptr(); \
+ const TCGv_i32 arg4_r32 = tcg_temp_new_i32(); \
+ \
+ assert(arg1 == arg2); \
+ tcg_gen_addi_ptr(arg1_ptr, cpu_env, arg1); \
+ tcg_gen_addi_ptr(arg3_ptr, cpu_env, arg3); \
+ tcg_gen_movi_i32(arg4_r32, arg4); \
+ gen_helper_ ## helper(cpu_env, arg1_ptr, arg3_ptr, arg4_r32); \
+ \
+ tcg_temp_free_ptr(arg1_ptr); \
+ tcg_temp_free_ptr(arg3_ptr); \
+ tcg_temp_free_i32(arg4_r32); \
+ }
+
static void gen_sse_ng(CPUX86State *env, DisasContext *s, int b)
{
enum {
--
2.20.1
- [Qemu-devel] [RFC PATCH v4 17/75] target/i386: introduce instruction operand infrastructure, (continued)
- [Qemu-devel] [RFC PATCH v4 17/75] target/i386: introduce instruction operand infrastructure, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 27/75] target/i386: introduce G*, R*, E* (general register) operands, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 23/75] target/i386: introduce operands for decoding modrm fields, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 25/75] target/i386: introduce Ib (immediate) operand, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 26/75] target/i386: introduce M* (memptr) operands, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 28/75] target/i386: introduce P*, N*, Q* (MMX) operands, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 30/75] target/i386: alias H* operands with the V* operands, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 29/75] target/i386: introduce H*, L*, V*, U*, W* (SSE/AVX) operands, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 31/75] target/i386: introduce code generators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 34/75] target/i386: introduce sse-opcode.inc.h, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 32/75] target/i386: introduce helper-based code generator macros,
Jan Bobek <=
- [Qemu-devel] [RFC PATCH v4 33/75] target/i386: introduce gvec-based code generator macros, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 39/75] target/i386: introduce SSE translators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 35/75] target/i386: introduce instruction translator macros, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 36/75] target/i386: introduce MMX translators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 38/75] target/i386: introduce MMX vector instructions to sse-opcode.inc.h, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 37/75] target/i386: introduce MMX code generators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 41/75] target/i386: introduce SSE vector instructions to sse-opcode.inc.h, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 45/75] target/i386: introduce SSE3 translators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 40/75] target/i386: introduce SSE code generators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 42/75] target/i386: introduce SSE2 translators, Jan Bobek, 2019/08/21