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[Qemu-devel] [RFC PATCH v4 27/75] target/i386: introduce G*, R*, E* (gen
From: |
Jan Bobek |
Subject: |
[Qemu-devel] [RFC PATCH v4 27/75] target/i386: introduce G*, R*, E* (general register) operands |
Date: |
Wed, 21 Aug 2019 13:29:03 -0400 |
These address the general-purpose register file. The corresponding
32-bit or 64-bit register is passed as the operand value.
Signed-off-by: Jan Bobek <address@hidden>
---
target/i386/translate.c | 88 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 46c41cc3be..d6d32c7f06 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -4944,6 +4944,94 @@ DEF_INSNOP_ALIAS(Mq, M)
DEF_INSNOP_ALIAS(Mdq, M)
DEF_INSNOP_ALIAS(Mqq, M)
+/*
+ * 32-bit general register operands
+ */
+DEF_INSNOP_LDST(Gd, tcg_i32, modrm_reg)
+DEF_INSNOP_LDST(Rd, tcg_i32, modrm_rm_direct)
+
+INSNOP_LDST(tcg_i32, modrm_reg)
+{
+ assert(0 <= ptr && ptr < CPU_NB_REGS);
+ if (is_write) {
+ tcg_gen_extu_i32_tl(cpu_regs[ptr], arg);
+ } else {
+ tcg_gen_trunc_tl_i32(arg, cpu_regs[ptr]);
+ }
+}
+INSNOP_LDST(tcg_i32, modrm_rm_direct)
+{
+ insnop_ldst(tcg_i32, modrm_reg)(env, s, is_write, arg, ptr);
+}
+
+DEF_INSNOP_LDST(MEd, tcg_i32, Md)
+DEF_INSNOP_EITHER(Ed, Rd, MEd)
+DEF_INSNOP_LDST(MRdMw, tcg_i32, Mw)
+DEF_INSNOP_EITHER(RdMw, Rd, MRdMw)
+DEF_INSNOP_LDST(MRdMb, tcg_i32, Mb)
+DEF_INSNOP_EITHER(RdMb, Rd, MRdMb)
+
+INSNOP_LDST(tcg_i32, Md)
+{
+ if (is_write) {
+ tcg_gen_qemu_st_i32(arg, ptr, s->mem_index, MO_LEUL);
+ } else {
+ tcg_gen_qemu_ld_i32(arg, ptr, s->mem_index, MO_LEUL);
+ }
+}
+INSNOP_LDST(tcg_i32, Mw)
+{
+ if (is_write) {
+ tcg_gen_qemu_st_i32(arg, ptr, s->mem_index, MO_LEUW);
+ } else {
+ tcg_gen_qemu_ld_i32(arg, ptr, s->mem_index, MO_LEUW);
+ }
+}
+INSNOP_LDST(tcg_i32, Mb)
+{
+ if (is_write) {
+ tcg_gen_qemu_st_i32(arg, ptr, s->mem_index, MO_UB);
+ } else {
+ tcg_gen_qemu_ld_i32(arg, ptr, s->mem_index, MO_UB);
+ }
+}
+
+/*
+ * 64-bit general register operands
+ */
+DEF_INSNOP_LDST(Gq, tcg_i64, modrm_reg)
+DEF_INSNOP_LDST(Rq, tcg_i64, modrm_rm_direct)
+
+INSNOP_LDST(tcg_i64, modrm_reg)
+{
+#ifdef TARGET_X86_64
+ assert(0 <= ptr && ptr < CPU_NB_REGS);
+ if (is_write) {
+ tcg_gen_mov_i64(cpu_regs[ptr], arg);
+ } else {
+ tcg_gen_mov_i64(arg, cpu_regs[ptr]);
+ }
+#else /* !TARGET_X86_64 */
+ g_assert_not_reached();
+#endif /* !TARGET_X86_64 */
+}
+INSNOP_LDST(tcg_i64, modrm_rm_direct)
+{
+ insnop_ldst(tcg_i64, modrm_reg)(env, s, is_write, arg, ptr);
+}
+
+DEF_INSNOP_LDST(MEq, tcg_i64, Mq)
+DEF_INSNOP_EITHER(Eq, Rq, MEq)
+
+INSNOP_LDST(tcg_i64, Mq)
+{
+ if (is_write) {
+ tcg_gen_qemu_st_i64(arg, ptr, s->mem_index, MO_LEQ);
+ } else {
+ tcg_gen_qemu_ld_i64(arg, ptr, s->mem_index, MO_LEQ);
+ }
+}
+
static void gen_sse_ng(CPUX86State *env, DisasContext *s, int b)
{
enum {
--
2.20.1
- [Qemu-devel] [RFC PATCH v4 16/75] target/i386: disable AVX/AVX2 cpuid bitchecks, (continued)
- [Qemu-devel] [RFC PATCH v4 16/75] target/i386: disable AVX/AVX2 cpuid bitchecks, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 14/75] target/i386: introduce aliases for some tcg_gvec operations, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 15/75] target/i386: introduce function check_cpuid, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 19/75] target/i386: introduce generic either-or operand, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 22/75] target/i386: introduce modrm operand, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 24/75] target/i386: introduce operand for direct-only r/m field, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 18/75] target/i386: introduce generic operand alias, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 20/75] target/i386: introduce generic load-store operand, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 21/75] target/i386: introduce tcg register operands, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 17/75] target/i386: introduce instruction operand infrastructure, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 27/75] target/i386: introduce G*, R*, E* (general register) operands,
Jan Bobek <=
- [Qemu-devel] [RFC PATCH v4 23/75] target/i386: introduce operands for decoding modrm fields, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 25/75] target/i386: introduce Ib (immediate) operand, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 26/75] target/i386: introduce M* (memptr) operands, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 28/75] target/i386: introduce P*, N*, Q* (MMX) operands, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 30/75] target/i386: alias H* operands with the V* operands, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 29/75] target/i386: introduce H*, L*, V*, U*, W* (SSE/AVX) operands, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 31/75] target/i386: introduce code generators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 34/75] target/i386: introduce sse-opcode.inc.h, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 32/75] target/i386: introduce helper-based code generator macros, Jan Bobek, 2019/08/21