Re: [Qemu-devel] [PATCH v2 37/68] target/arm: Convert PLI, PLD, PLDW

[Philippe Mathieu-Daudé]

On 8/19/19 11:37 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target/arm/translate.c       | 37 +++++++++++++++++++-----------------
>  target/arm/a32-uncond.decode | 10 ++++++++++
>  2 files changed, 30 insertions(+), 17 deletions(-)
> 
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 46e88d1d17..a30a9bb4e0 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -10136,6 +10136,26 @@ static bool trans_SETEND(DisasContext *s, arg_SETEND 
> *a)
>      return true;
>  }
>  
> +/*
> + * Preload instructions
> + * All are nops, contingent on the appropriate arch level.
> + */
> +
> +static bool trans_PLD(DisasContext *s, arg_PLD *a)
> +{
> +    return ENABLE_ARCH_5TE;

Excellent :)

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>

> +}
> +
> +static bool trans_PLDW(DisasContext *s, arg_PLD *a)
> +{
> +    return arm_dc_feature(s, ARM_FEATURE_V7MP);
> +}
> +
> +static bool trans_PLI(DisasContext *s, arg_PLD *a)
> +{
> +    return ENABLE_ARCH_7;
> +}
> +
>  /*
>   * Legacy decoder.
>   */
> @@ -10196,23 +10216,6 @@ static void disas_arm_insn(DisasContext *s, unsigned 
> int insn)
>              }
>              return;
>          }
> -        if (((insn & 0x0f30f000) == 0x0510f000) ||
> -            ((insn & 0x0f30f010) == 0x0710f000)) {
> -            if ((insn & (1 << 22)) == 0) {
> -                /* PLDW; v7MP */
> -                if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) {
> -                    goto illegal_op;
> -                }
> -            }
> -            /* Otherwise PLD; v5TE+ */
> -            ARCH(5TE);
> -            return;
> -        }
> -        if (((insn & 0x0f70f000) == 0x0450f000) ||
> -            ((insn & 0x0f70f010) == 0x0650f000)) {
> -            ARCH(7);
> -            return; /* PLI; V7 */
> -        }
>          if (((insn & 0x0f700000) == 0x04100000) ||
>              ((insn & 0x0f700010) == 0x06100000)) {
>              if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) {
> diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode
> index d5ed48f0fd..aed381cb8e 100644
> --- a/target/arm/a32-uncond.decode
> +++ b/target/arm/a32-uncond.decode
> @@ -54,3 +54,13 @@ SB               1111 0101 0111 1111 1111 0000 0111 0000
>  
>  # Set Endianness
>  SETEND           1111 0001 0000 0001 0000 00 E:1 0 0000 0000  &setend
> +
> +# Preload instructions
> +
> +PLD              1111 0101 -101 ---- 1111 ---- ---- ----    # (imm, lit) 5te
> +PLDW             1111 0101 -001 ---- 1111 ---- ---- ----    # (imm, lit) 7mp
> +PLI              1111 0100 -101 ---- 1111 ---- ---- ----    # (imm, lit) 7
> +
> +PLD              1111 0111 -101 ---- 1111 ----- -- 0 ----   # (register) 5te
> +PLDW             1111 0111 -001 ---- 1111 ----- -- 0 ----   # (register) 7mp
> +PLI              1111 0110 -101 ---- 1111 ----- -- 0 ----   # (register) 7
>