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[Qemu-devel] [PATCH v4 08/28] riscv: sifive_e: prci: Fix a typo of hfxos
From: |
Bin Meng |
Subject: |
[Qemu-devel] [PATCH v4 08/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming |
Date: |
Sun, 18 Aug 2019 22:11:41 -0700 |
For hfxosccfg register programming, SIFIVE_E_PRCI_HFXOSCCFG_RDY and
SIFIVE_E_PRCI_HFXOSCCFG_EN should be used.
Signed-off-by: Bin Meng <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_e_prci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c
index e87a3ce..603a54b 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/riscv/sifive_e_prci.c
@@ -89,7 +89,7 @@ static void sifive_e_prci_init(Object *obj)
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
s->hfrosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN);
- s->hfxosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN);
+ s->hfxosccfg = (SIFIVE_E_PRCI_HFXOSCCFG_RDY | SIFIVE_E_PRCI_HFXOSCCFG_EN);
s->pllcfg = (SIFIVE_E_PRCI_PLLCFG_REFSEL | SIFIVE_E_PRCI_PLLCFG_BYPASS |
SIFIVE_E_PRCI_PLLCFG_LOCK);
s->plloutdiv = SIFIVE_E_PRCI_PLLOUTDIV_DIV1;
--
2.7.4
- [Qemu-devel] [PATCH v4 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 01/28] riscv: hw: Remove superfluous "linux, phandle" property, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 03/28] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 04/28] riscv: hw: Change create_fdt() to return void, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 05/28] riscv: roms: Remove executable attribute of opensbi images, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 06/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 07/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 08/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming,
Bin Meng <=
- [Qemu-devel] [PATCH v4 09/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 12/28] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 16/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 15/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 17/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 14/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 22/28] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/08/19