[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v4 06/28] riscv: sifive_u: Remove the unnecessary in
From: |
Bin Meng |
Subject: |
[Qemu-devel] [PATCH v4 06/28] riscv: sifive_u: Remove the unnecessary include of prci header |
Date: |
Sun, 18 Aug 2019 22:11:39 -0700 |
sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e22803b..3f58f61 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -39,7 +39,6 @@
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_uart.h"
-#include "hw/riscv/sifive_prci.h"
#include "hw/riscv/sifive_u.h"
#include "hw/riscv/boot.h"
#include "chardev/char.h"
--
2.7.4
- [Qemu-devel] [PATCH v4 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 01/28] riscv: hw: Remove superfluous "linux, phandle" property, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 03/28] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 04/28] riscv: hw: Change create_fdt() to return void, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 05/28] riscv: roms: Remove executable attribute of opensbi images, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 06/28] riscv: sifive_u: Remove the unnecessary include of prci header,
Bin Meng <=
- [Qemu-devel] [PATCH v4 07/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 08/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 09/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 12/28] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 16/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 15/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 17/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 14/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/19
- [Qemu-devel] [PATCH v4 22/28] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/19