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Re: [Qemu-devel] [PATCH-for-4.2 v1 3/6] s390x/tcg: Flush the TLB of all
From: |
Cornelia Huck |
Subject: |
Re: [Qemu-devel] [PATCH-for-4.2 v1 3/6] s390x/tcg: Flush the TLB of all CPUs on SSKE and RRBE |
Date: |
Tue, 13 Aug 2019 15:42:32 +0200 |
On Mon, 12 Aug 2019 13:27:34 +0200
David Hildenbrand <address@hidden> wrote:
> Whenever we modify a storage key, we shuld flush the TLBs of all CPUs,
> so the MMU fault handling code can properly consider the changed storage
> key (to e.g., properly set the reference and change bit on the next
> accesses).
>
> These functions are barely used in modern Linux guests, so the performance
> implications are neglectable for now.
>
> This is a preparation for better reference and change bit handling for
> TCG, which will require more MMU changes.
>
> Signed-off-by: David Hildenbrand <address@hidden>
> ---
> target/s390x/mem_helper.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
> index 29d9eaa5b7..ed54265e03 100644
> --- a/target/s390x/mem_helper.c
> +++ b/target/s390x/mem_helper.c
> @@ -1815,6 +1815,8 @@ void HELPER(sske)(CPUS390XState *env, uint64_t r1,
> uint64_t r2)
>
> key = (uint8_t) r1;
> skeyclass->set_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key);
> + /* TODO: Flush only entries with this target address */
> + tlb_flush_all_cpus_synced(env_cpu(env));
> }
>
> /* reset reference bit extended */
> @@ -1843,6 +1845,8 @@ uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2)
> if (skeyclass->set_skeys(ss, r2 / TARGET_PAGE_SIZE, 1, &key)) {
> return 0;
> }
> + /* TODO: Flush only entries with this target address */
> + tlb_flush_all_cpus_synced(env_cpu(env));
>
> /*
> * cc
Seems reasonable.
Reviewed-by: Cornelia Huck <address@hidden>
- Re: [Qemu-devel] [qemu-s390x] [PATCH-for-4.2 v1 1/6] s390x/mmu: ASC selection in s390_cpu_get_phys_page_debug(), (continued)
Re: [Qemu-devel] [PATCH-for-4.2 v1 1/6] s390x/mmu: ASC selection in s390_cpu_get_phys_page_debug(), Cornelia Huck, 2019/08/13
[Qemu-devel] [PATCH-for-4.2 v1 2/6] s390x/tcg: Rework MMU selection for instruction fetches, David Hildenbrand, 2019/08/12
Re: [Qemu-devel] [PATCH-for-4.2 v1 2/6] s390x/tcg: Rework MMU selection for instruction fetches, Cornelia Huck, 2019/08/13
[Qemu-devel] [PATCH-for-4.2 v1 3/6] s390x/tcg: Flush the TLB of all CPUs on SSKE and RRBE, David Hildenbrand, 2019/08/12
- Re: [Qemu-devel] [PATCH-for-4.2 v1 3/6] s390x/tcg: Flush the TLB of all CPUs on SSKE and RRBE,
Cornelia Huck <=
[Qemu-devel] [PATCH-for-4.2 v1 4/6] s390x/mmu: Trace the right value if setting/getting the storage key fails, David Hildenbrand, 2019/08/12
[Qemu-devel] [PATCH-for-4.2 v1 5/6] s390x/mmu: Better storage key reference and change bit handling, David Hildenbrand, 2019/08/12
[Qemu-devel] [PATCH-for-4.2 v1 6/6] s390x/mmu: Factor out storage key handling, David Hildenbrand, 2019/08/12