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[Qemu-devel] [PATCH v3 12/28] riscv: sifive_e: prci: Fix a typo of hfxos
From: |
Bin Meng |
Subject: |
[Qemu-devel] [PATCH v3 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming |
Date: |
Sun, 11 Aug 2019 01:06:45 -0700 |
It should use SIFIVE_PRCI_HFXOSCCFG_RDY and SIFIVE_PRCI_HFXOSCCFG_EN
for hfxosccfg register programming.
Signed-off-by: Bin Meng <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
---
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_e_prci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c
index acb914d..c906f11 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/riscv/sifive_e_prci.c
@@ -89,7 +89,7 @@ static void sifive_prci_init(Object *obj)
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
- s->hfxosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
+ s->hfxosccfg = (SIFIVE_PRCI_HFXOSCCFG_RDY | SIFIVE_PRCI_HFXOSCCFG_EN);
s->pllcfg = (SIFIVE_PRCI_PLLCFG_REFSEL | SIFIVE_PRCI_PLLCFG_BYPASS |
SIFIVE_PRCI_PLLCFG_LOCK);
s->plloutdiv = SIFIVE_PRCI_PLLOUTDIV_DIV1;
--
2.7.4
- [Qemu-devel] [PATCH v3 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, (continued)
- [Qemu-devel] [PATCH v3 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 05/28] riscv: hart: Support heterogeneous harts population, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 07/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 08/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 10/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 09/28] riscv: sifive_u: Update UART base addresses and IRQs, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming,
Bin Meng <=
- [Qemu-devel] [PATCH v3 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 13/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 14/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 17/28] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 16/28] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 18/28] riscv: hw: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/11