[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v2 09/28] riscv: sifive_u: Update UART base addresse
From: |
Bin Meng |
Subject: |
[Qemu-devel] [PATCH v2 09/28] riscv: sifive_u: Update UART base addresses |
Date: |
Wed, 7 Aug 2019 00:45:05 -0700 |
This updates the UART base address to match the hardware.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Jonathan Behrens <address@hidden>
Acked-by: Alistair Francis <address@hidden>
---
Changes in v2: None
hw/riscv/sifive_u.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index fe8dd3e..ea45e77 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -61,8 +61,8 @@ static const struct MemmapEntry {
[SIFIVE_U_MROM] = { 0x1000, 0x11000 },
[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
- [SIFIVE_U_UART0] = { 0x10013000, 0x1000 },
- [SIFIVE_U_UART1] = { 0x10023000, 0x1000 },
+ [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
+ [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
[SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
};
--
2.7.4
- Re: [Qemu-devel] [PATCH v2 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, (continued)
- [Qemu-devel] [PATCH v2 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 10/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 04/28] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 08/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 05/28] riscv: hart: Support heterogeneous harts population, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 09/28] riscv: sifive_u: Update UART base addresses,
Bin Meng <=
- [Qemu-devel] [PATCH v2 07/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/07
- Re: [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Alistair Francis, 2019/08/09