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[Qemu-devel] [PATCH v2 04/28] riscv: hart: Extract hart realize to a sep
From: |
Bin Meng |
Subject: |
[Qemu-devel] [PATCH v2 04/28] riscv: hart: Extract hart realize to a separate routine |
Date: |
Wed, 7 Aug 2019 00:45:00 -0700 |
Currently riscv_harts_realize() creates all harts based on the
same cpu type given in the hart array property. With current
implementation it can only create symmetric harts. Exact the
hart realize to a separate routine in preparation for supporting
heterogeneous hart arrays.
Signed-off-by: Bin Meng <address@hidden>
---
Changes in v2: None
hw/riscv/riscv_hart.c | 31 +++++++++++++++++++------------
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index ca69a1b..3dd1c6a 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -37,26 +37,33 @@ static void riscv_harts_cpu_reset(void *opaque)
cpu_reset(CPU(cpu));
}
+static void riscv_hart_realize(RISCVHartArrayState *s, int hart,
+ char *cpu_type, Error **errp)
+{
+ Error *err = NULL;
+
+ object_initialize_child(OBJECT(s), "harts[*]", &s->harts[hart],
+ sizeof(RISCVCPU), cpu_type,
+ &error_abort, NULL);
+ s->harts[hart].env.mhartid = hart;
+ qemu_register_reset(riscv_harts_cpu_reset, &s->harts[hart]);
+ object_property_set_bool(OBJECT(&s->harts[hart]), true,
+ "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+}
+
static void riscv_harts_realize(DeviceState *dev, Error **errp)
{
RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
- Error *err = NULL;
int n;
s->harts = g_new0(RISCVCPU, s->num_harts);
for (n = 0; n < s->num_harts; n++) {
- object_initialize_child(OBJECT(s), "harts[*]", &s->harts[n],
- sizeof(RISCVCPU), s->cpu_type,
- &error_abort, NULL);
- s->harts[n].env.mhartid = n;
- qemu_register_reset(riscv_harts_cpu_reset, &s->harts[n]);
- object_property_set_bool(OBJECT(&s->harts[n]), true,
- "realized", &err);
- if (err) {
- error_propagate(errp, err);
- return;
- }
+ riscv_hart_realize(s, n, s->cpu_type, errp);
}
}
--
2.7.4
- [Qemu-devel] [PATCH v2 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 01/28] riscv: hw: Remove superfluous "linux, phandle" property, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 10/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 04/28] riscv: hart: Extract hart realize to a separate routine,
Bin Meng <=
- [Qemu-devel] [PATCH v2 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 08/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 05/28] riscv: hart: Support heterogeneous harts population, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 09/28] riscv: sifive_u: Update UART base addresses, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 07/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/07