[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [RFC PATCH 16/20] hw/i386/pc: Account for SGX EPC sections
From: |
Sean Christopherson |
Subject: |
[Qemu-devel] [RFC PATCH 16/20] hw/i386/pc: Account for SGX EPC sections when calculating device memory |
Date: |
Tue, 6 Aug 2019 11:56:45 -0700 |
Add helpers to detect if SGX EPC exists above 4g, and if so, where SGX
EPC above 4g ends. Use the helpers to adjust the device memory range
if SGX EPC exists above 4g.
Note that SGX EPC is currently hardcoded to reside above 4g.
Signed-off-by: Sean Christopherson <address@hidden>
---
hw/i386/pc.c | 10 +++++++++-
include/hw/i386/sgx-epc.h | 12 ++++++++++++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 8c8b404799..614d464394 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1882,8 +1882,14 @@ void pc_memory_init(PCMachineState *pcms,
exit(EXIT_FAILURE);
}
+ if (sgx_epc_above_4g(pcms->sgx_epc)) {
+ machine->device_memory->base = sgx_epc_above_4g_end(pcms->sgx_epc);
+ } else {
+ machine->device_memory->base =
+ 0x100000000ULL + pcms->above_4g_mem_size;
+ }
machine->device_memory->base =
- ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
+ ROUND_UP(machine->device_memory->base, 1 * GiB);
if (pcmc->enforce_aligned_dimm) {
/* size device region assuming 1G page max alignment per slot */
@@ -1962,6 +1968,8 @@ uint64_t pc_pci_hole64_start(void)
if (!pcmc->broken_reserved_end) {
hole64_start += memory_region_size(&ms->device_memory->mr);
}
+ } else if (sgx_epc_above_4g(pcms->sgx_epc)) {
+ hole64_start = sgx_epc_above_4g_end(pcms->sgx_epc);
} else {
hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
}
diff --git a/include/hw/i386/sgx-epc.h b/include/hw/i386/sgx-epc.h
index 91ed4773e3..136449cd80 100644
--- a/include/hw/i386/sgx-epc.h
+++ b/include/hw/i386/sgx-epc.h
@@ -60,4 +60,16 @@ extern int sgx_epc_enabled;
void pc_machine_init_sgx_epc(PCMachineState *pcms);
int sgx_epc_get_section(int section_nr, uint64_t *addr, uint64_t *size);
+static inline bool sgx_epc_above_4g(SGXEPCState *sgx_epc)
+{
+ return sgx_epc != NULL;
+}
+
+static inline uint64_t sgx_epc_above_4g_end(SGXEPCState *sgx_epc)
+{
+ assert(sgx_epc != NULL && sgx_epc->base >= 0x100000000ULL);
+
+ return sgx_epc->base + sgx_epc->size;
+}
+
#endif
--
2.22.0
- [Qemu-devel] [RFC PATCH 14/20] i386: Adjust min CPUID level to 0x12 when SGX is enabled, (continued)
- [Qemu-devel] [RFC PATCH 14/20] i386: Adjust min CPUID level to 0x12 when SGX is enabled, Sean Christopherson, 2019/08/06
- [Qemu-devel] [RFC PATCH 06/20] i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX, Sean Christopherson, 2019/08/06
- [Qemu-devel] [RFC PATCH 12/20] i386: kvm: Add support for exposing PROVISIONKEY to guest, Sean Christopherson, 2019/08/06
- [Qemu-devel] [RFC PATCH 07/20] i386: Add SGX CPUID leaf FEAT_SGX_12_1_EBX, Sean Christopherson, 2019/08/06
- [Qemu-devel] [RFC PATCH 11/20] linux-headers: Add temporary placeholder for KVM_CAP_SGX_ATTRIBUTE, Sean Christopherson, 2019/08/06
- [Qemu-devel] [RFC PATCH 02/20] i386: Add 'sgx-epc' device to expose EPC sections to guest, Sean Christopherson, 2019/08/06
- [Qemu-devel] [RFC PATCH 03/20] vl: Add "sgx-epc" option to expose SGX EPC sections to guest, Sean Christopherson, 2019/08/06
- [Qemu-devel] [RFC PATCH 20/20] i440fx: Add support for SGX EPC, Sean Christopherson, 2019/08/06
- [Qemu-devel] [RFC PATCH 18/20] i386: acpi: Add SGX EPC entry to ACPI tables, Sean Christopherson, 2019/08/06
- [Qemu-devel] [RFC PATCH 16/20] hw/i386/pc: Account for SGX EPC sections when calculating device memory,
Sean Christopherson <=
- [Qemu-devel] [RFC PATCH 19/20] q35: Add support for SGX EPC, Sean Christopherson, 2019/08/06
- [Qemu-devel] [RFC PATCH 13/20] i386: Propagate SGX CPUID sub-leafs to KVM, Sean Christopherson, 2019/08/06
- Re: [Qemu-devel] [RFC PATCH 00/20] i386: Add support for Intel SGX, no-reply, 2019/08/06
- Re: [Qemu-devel] [RFC PATCH 00/20] i386: Add support for Intel SGX, no-reply, 2019/08/06