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Re: [Qemu-devel] [PATCH 02/28] riscv: hw: Use qemu_fdt_setprop_cell() fo
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell |
Date: |
Mon, 5 Aug 2019 17:13:45 -0700 |
On Mon, Aug 5, 2019 at 9:04 AM Bin Meng <address@hidden> wrote:
>
> Some of the properties only have 1 cell so we should use
> qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells().
>
> Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 16 ++++++++--------
> hw/riscv/virt.c | 24 ++++++++++++------------
> 2 files changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index ef36948..623ee64 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -182,7 +182,7 @@ static void create_fdt(SiFiveUState *s, const struct
> MemmapEntry *memmap,
> qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
> qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
> qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
> - qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
> + qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
> plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
> g_free(cells);
> g_free(nodename);
> @@ -207,20 +207,20 @@ static void create_fdt(SiFiveUState *s, const struct
> MemmapEntry *memmap,
> 0x0, memmap[SIFIVE_U_GEM].size);
> qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
> qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
> - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
> - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
> qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> ethclk_phandle, ethclk_phandle, ethclk_phandle);
> qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names,
> sizeof(ethclk_names));
> - qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1);
> - qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0);
> + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
> + qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
> g_free(nodename);
>
> nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
> (long)memmap[SIFIVE_U_GEM].base);
> qemu_fdt_add_subnode(fdt, nodename);
> - qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0);
> + qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
> g_free(nodename);
>
> nodename = g_strdup_printf("/soc/uart@%lx",
> @@ -232,8 +232,8 @@ static void create_fdt(SiFiveUState *s, const struct
> MemmapEntry *memmap,
> 0x0, memmap[SIFIVE_U_UART0].size);
> qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
> SIFIVE_U_CLOCK_FREQ / 2);
> - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
> - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
>
> qemu_fdt_add_subnode(fdt, "/chosen");
> qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 00be05a..127f005 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -233,8 +233,8 @@ static void *create_fdt(RISCVVirtState *s, const struct
> MemmapEntry *memmap,
> nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
> (long)memmap[VIRT_PLIC].base);
> qemu_fdt_add_subnode(fdt, nodename);
> - qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
> - FDT_PLIC_ADDR_CELLS);
> + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
> + FDT_PLIC_ADDR_CELLS);
> qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
> FDT_PLIC_INT_CELLS);
> qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
> @@ -247,7 +247,7 @@ static void *create_fdt(RISCVVirtState *s, const struct
> MemmapEntry *memmap,
> qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
> qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
> qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
> - qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
> + qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
> plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
> g_free(cells);
> g_free(nodename);
> @@ -260,19 +260,19 @@ static void *create_fdt(RISCVVirtState *s, const struct
> MemmapEntry *memmap,
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
> 0x0, memmap[VIRT_VIRTIO].size);
> - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent",
> plic_phandle);
> - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent",
> plic_phandle);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
> g_free(nodename);
> }
>
> nodename = g_strdup_printf("/soc/pci@%lx",
> (long) memmap[VIRT_PCIE_ECAM].base);
> qemu_fdt_add_subnode(fdt, nodename);
> - qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
> - FDT_PCI_ADDR_CELLS);
> - qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells",
> - FDT_PCI_INT_CELLS);
> - qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2);
> + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
> + FDT_PCI_ADDR_CELLS);
> + qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
> + FDT_PCI_INT_CELLS);
> + qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2);
> qemu_fdt_setprop_string(fdt, nodename, "compatible",
> "pci-host-ecam-generic");
> qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
> @@ -309,8 +309,8 @@ static void *create_fdt(RISCVVirtState *s, const struct
> MemmapEntry *memmap,
> 0x0, memmap[VIRT_UART0].base,
> 0x0, memmap[VIRT_UART0].size);
> qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
> - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent",
> plic_phandle);
> - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", UART0_IRQ);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ);
>
> qemu_fdt_add_subnode(fdt, "/chosen");
> qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
> --
> 2.7.4
>
>
- [Qemu-devel] [PATCH 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 01/28] riscv: hw: Remove superfluous "linux, phandle" property, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/05
- Re: [Qemu-devel] [PATCH 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell,
Alistair Francis <=
- [Qemu-devel] [PATCH 04/28] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 05/28] riscv: hart: Support heterogeneous harts population, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 09/28] riscv: sifive_u: Update UART base addresses, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 08/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/05