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Re: [Qemu-devel] [PATCH 01/28] riscv: hw: Remove superfluous "linux, pha
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH 01/28] riscv: hw: Remove superfluous "linux, phandle" property |
Date: |
Mon, 5 Aug 2019 17:11:37 -0700 |
On Mon, Aug 5, 2019 at 9:06 AM Bin Meng <address@hidden> wrote:
>
> "linux,phandle" property is optional. Remove all instances in the
> sifive_u and virt machine device tree.
>
> Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 3 ---
> hw/riscv/virt.c | 3 ---
> 2 files changed, 6 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 71b8083..ef36948 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -125,7 +125,6 @@ static void create_fdt(SiFiveUState *s, const struct
> MemmapEntry *memmap,
> qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
> qemu_fdt_add_subnode(fdt, intc);
> qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
> - qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle);
> qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
> qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
> qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
> @@ -184,7 +183,6 @@ static void create_fdt(SiFiveUState *s, const struct
> MemmapEntry *memmap,
> qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
> qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
> qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
> - qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
> plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
> g_free(cells);
> g_free(nodename);
> @@ -197,7 +195,6 @@ static void create_fdt(SiFiveUState *s, const struct
> MemmapEntry *memmap,
> qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
> SIFIVE_U_GEM_CLOCK_FREQ);
> qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle);
> - qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", ethclk_phandle);
> ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
> g_free(nodename);
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 25faf3b..00be05a 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -170,11 +170,9 @@ static void *create_fdt(RISCVVirtState *s, const struct
> MemmapEntry *memmap,
> qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
> qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
> qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
> - qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", cpu_phandle);
> intc_phandle = phandle++;
> qemu_fdt_add_subnode(fdt, intc);
> qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
> - qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", intc_phandle);
> qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
> qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
> qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
> @@ -250,7 +248,6 @@ static void *create_fdt(RISCVVirtState *s, const struct
> MemmapEntry *memmap,
> qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
> qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
> qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
> - qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
> plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
> g_free(cells);
> g_free(nodename);
> --
> 2.7.4
>
>
- [Qemu-devel] [PATCH 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 01/28] riscv: hw: Remove superfluous "linux, phandle" property, Bin Meng, 2019/08/05
- Re: [Qemu-devel] [PATCH 01/28] riscv: hw: Remove superfluous "linux, phandle" property,
Alistair Francis <=
- [Qemu-devel] [PATCH 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 04/28] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 05/28] riscv: hart: Support heterogeneous harts population, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 09/28] riscv: sifive_u: Update UART base addresses, Bin Meng, 2019/08/05