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[Qemu-devel] [PATCH v3 34/34] target/arm: generate a custom MIDR for -cp
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 34/34] target/arm: generate a custom MIDR for -cpu max |
Date: |
Sat, 3 Aug 2019 11:48:00 -0700 |
From: Alex Bennée <address@hidden>
While most features are now detected by probing the ID_* registers
kernels can (and do) use MIDR_EL1 for working out of they have to
apply errata. This can trip up warnings in the kernel as it tries to
work out if it should apply workarounds to features that don't
actually exist in the reported CPU type.
Avoid this problem by synthesising our own MIDR value.
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu.h | 6 ++++++
target/arm/cpu64.c | 19 +++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d7c5a123a3..6e4c97d398 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1605,6 +1605,12 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
/*
* System register ID fields.
*/
+FIELD(MIDR_EL1, REVISION, 0, 4)
+FIELD(MIDR_EL1, PARTNUM, 4, 12)
+FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
+FIELD(MIDR_EL1, VARIANT, 20, 4)
+FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
+
FIELD(ID_ISAR0, SWAP, 0, 4)
FIELD(ID_ISAR0, BITCOUNT, 4, 4)
FIELD(ID_ISAR0, BITFIELD, 8, 4)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index b1bb394c6d..3a1e98a18e 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -296,6 +296,25 @@ static void aarch64_max_initfn(Object *obj)
uint32_t u;
aarch64_a57_initfn(obj);
+ /*
+ * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a
real
+ * one and try to apply errata workarounds or use impdef features we
+ * don't provide.
+ * An IMPLEMENTER field of 0 means "reserved for software use";
+ * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
+ * to see which features are present";
+ * the VARIANT, PARTNUM and REVISION fields are all implementation
+ * defined and we choose to define PARTNUM just in case guest
+ * code needs to distinguish this QEMU CPU from other software
+ * implementations, though this shouldn't be needed.
+ */
+ t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
+ t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
+ t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
+ t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
+ t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
+ cpu->midr = t;
+
t = cpu->isar.id_aa64isar0;
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
--
2.17.1
- [Qemu-devel] [PATCH v3 20/34] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2, (continued)
- [Qemu-devel] [PATCH v3 20/34] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 22/34] target/arm: Add regime_has_2_ranges, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 21/34] target/arm: Reorganize ARMMMUIdx, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 24/34] target/arm: Update arm_sctlr for VHE, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 27/34] target/arm: Install asids for E2&0 translation regime, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 25/34] target/arm: Update aa64_zva_access for EL2, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 26/34] target/arm: Update ctr_el0_access for EL2, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 28/34] target/arm: Flush tlbs for E2&0 translation regime, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 30/34] target/arm: Update regime_is_user for EL2&0, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 32/34] target/arm: Enable ARMv8.1-VHE in -cpu max, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 34/34] target/arm: generate a custom MIDR for -cpu max,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 31/34] target/arm: Update {fp, sve}_exception_el for VHE, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 29/34] target/arm: Update arm_phys_excp_target_el for TGE, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 33/34] target/arm: check TGE and E2H flags for EL0 pauth traps, Richard Henderson, 2019/08/03
- Re: [Qemu-devel] [PATCH v3 00/34] target/arm: Implement ARMv8.1-VHE, Alex Bennée, 2019/08/05