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[Qemu-devel] [PATCH v3 24/34] target/arm: Update arm_sctlr for VHE
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 24/34] target/arm: Update arm_sctlr for VHE |
Date: |
Sat, 3 Aug 2019 11:47:50 -0700 |
Use the correct sctlr for EL2&0 regime. Due to header ordering,
and where arm_mmu_idx is declared, we need to move the function
out of line. Use the function in many more places in order to
select the correct control.
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
v5: Use arm_mmu_idx() to avoid incorrectly replicating the el2&0
condition therein. Drop the change to cpu_get_dump_info, as
that needs a more significant rethink of hard-coded oddness.
---
target/arm/cpu.h | 11 +----------
target/arm/helper-a64.c | 2 +-
target/arm/helper.c | 14 ++++++++++++--
target/arm/pauth_helper.c | 9 +--------
4 files changed, 15 insertions(+), 21 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 8d90a4fc4d..d7c5a123a3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3096,16 +3096,7 @@ static inline bool arm_sctlr_b(CPUARMState *env)
(env->cp15.sctlr_el[1] & SCTLR_B) != 0;
}
-static inline uint64_t arm_sctlr(CPUARMState *env, int el)
-{
- if (el == 0) {
- /* FIXME: ARMv8.1-VHE S2 translation regime. */
- return env->cp15.sctlr_el[1];
- } else {
- return env->cp15.sctlr_el[el];
- }
-}
-
+uint64_t arm_sctlr(CPUARMState *env, int el);
/* Return true if the processor is in big-endian mode. */
static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 060699b901..3bf1b731e7 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -70,7 +70,7 @@ static void daif_check(CPUARMState *env, uint32_t op,
uint32_t imm, uintptr_t ra)
{
/* DAIF update to PSTATE. This is OK from EL0 only if UMA is set. */
- if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
+ if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) {
raise_exception_ra(env, EXCP_UDEF,
syn_aa64_sysregtrap(0, extract32(op, 0, 3),
extract32(op, 3, 3), 4,
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a570d43232..9e9d2ce99b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3867,7 +3867,7 @@ static void aa64_fpsr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo
*ri,
bool isread)
{
- if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
+ if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) {
return CP_ACCESS_TRAP;
}
return CP_ACCESS_OK;
@@ -3886,7 +3886,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState
*env,
/* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
* SCTLR_EL1.UCI is set.
*/
- if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
+ if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UCI)) {
return CP_ACCESS_TRAP;
}
return CP_ACCESS_OK;
@@ -8718,6 +8718,16 @@ static uint32_t regime_el(CPUARMState *env, ARMMMUIdx
mmu_idx)
}
}
+uint64_t arm_sctlr(CPUARMState *env, int el)
+{
+ /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
+ if (el == 0) {
+ ARMMMUIdx mmu_idx = arm_mmu_idx(env);
+ el = (mmu_idx == ARMMMUIdx_EL20_0 ? 2 : 1);
+ }
+ return env->cp15.sctlr_el[el];
+}
+
#ifndef CONFIG_USER_ONLY
/* Return the SCTLR value which controls this address translation regime */
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
index d3194f2043..42c9141bb7 100644
--- a/target/arm/pauth_helper.c
+++ b/target/arm/pauth_helper.c
@@ -386,14 +386,7 @@ static void pauth_check_trap(CPUARMState *env, int el,
uintptr_t ra)
static bool pauth_key_enabled(CPUARMState *env, int el, uint32_t bit)
{
- uint32_t sctlr;
- if (el == 0) {
- /* FIXME: ARMv8.1-VHE S2 translation regime. */
- sctlr = env->cp15.sctlr_el[1];
- } else {
- sctlr = env->cp15.sctlr_el[el];
- }
- return (sctlr & bit) != 0;
+ return (arm_sctlr(env, el) & bit) != 0;
}
uint64_t HELPER(pacia)(CPUARMState *env, uint64_t x, uint64_t y)
--
2.17.1
- [Qemu-devel] [PATCH v3 13/34] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask, (continued)
- [Qemu-devel] [PATCH v3 13/34] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 15/34] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_*, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 16/34] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 17/34] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 19/34] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 18/34] target/arm: Rename ARMMMUIdx_S1SE* to ARMMMUIdx_SE*, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 23/34] target/arm: Update arm_mmu_idx for VHE, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 20/34] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 22/34] target/arm: Add regime_has_2_ranges, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 21/34] target/arm: Reorganize ARMMMUIdx, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 24/34] target/arm: Update arm_sctlr for VHE,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 27/34] target/arm: Install asids for E2&0 translation regime, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 25/34] target/arm: Update aa64_zva_access for EL2, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 26/34] target/arm: Update ctr_el0_access for EL2, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 28/34] target/arm: Flush tlbs for E2&0 translation regime, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 30/34] target/arm: Update regime_is_user for EL2&0, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 32/34] target/arm: Enable ARMv8.1-VHE in -cpu max, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 34/34] target/arm: generate a custom MIDR for -cpu max, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 31/34] target/arm: Update {fp, sve}_exception_el for VHE, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 29/34] target/arm: Update arm_phys_excp_target_el for TGE, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 33/34] target/arm: check TGE and E2H flags for EL0 pauth traps, Richard Henderson, 2019/08/03