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[Qemu-devel] [PULL 11/23] target-arm: Handle SMC/HVC undef-if-no-ELx in
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 11/23] target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers |
Date: |
Fri, 24 Oct 2014 12:37:17 +0100 |
SMC must UNDEF if EL3 is not implemented; similarly HVC UNDEFs
if EL2 is not implemented. Move the handling of this from
translate-a64.c into the pre_smc and pre_hvc helper functions.
This is necessary because use of these instructions for PSCI
takes precedence over this UNDEF case, and we can't tell if
this is a PSCI call until runtime.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
target-arm/op_helper.c | 17 ++++++++++-------
target-arm/translate-a64.c | 4 ++--
2 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 03ac92a..5652096 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -392,10 +392,11 @@ void HELPER(pre_hvc)(CPUARMState *env)
bool secure = false;
bool undef;
- /* We've already checked that EL2 exists at translation time.
- * EL3.HCE has priority over EL2.HCD.
- */
- if (arm_feature(env, ARM_FEATURE_EL3)) {
+ if (!arm_feature(env, ARM_FEATURE_EL2)) {
+ /* If EL2 doesn't exist, HVC always UNDEFs */
+ undef = true;
+ } else if (arm_feature(env, ARM_FEATURE_EL3)) {
+ /* EL3.HCE has priority over EL2.HCD. */
undef = !(env->cp15.scr_el3 & SCR_HCE);
} else {
undef = env->cp15.hcr_el2 & HCR_HCD;
@@ -429,13 +430,15 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
*/
bool undef = is_a64(env) ? smd : (!secure && smd);
- /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. */
- if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
+ if (!arm_feature(env, ARM_FEATURE_EL3)) {
+ /* If we have no EL3 then SMC always UNDEFs */
+ undef = true;
+ } else if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
+ /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. */
env->exception.syndrome = syndrome;
raise_exception(env, EXCP_HYP_TRAP);
}
- /* We've already checked that EL3 exists at translation time. */
if (undef) {
env->exception.syndrome = syn_uncategorized();
raise_exception(env, EXCP_UDEF);
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 35ae3ea..b15261b 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1485,7 +1485,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16));
break;
case 2:
- if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_pl == 0) {
+ if (s->current_pl == 0) {
unallocated_encoding(s);
break;
}
@@ -1498,7 +1498,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16));
break;
case 3:
- if (!arm_dc_feature(s, ARM_FEATURE_EL3) || s->current_pl == 0) {
+ if (s->current_pl == 0) {
unallocated_encoding(s);
break;
}
--
1.9.1
- [Qemu-devel] [PULL 00/23] target-arm queue, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 22/23] target-arm: make arm_current_el() return EL3, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 16/23] target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any", Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 15/23] target-arm: Correct sense of the DCZID DZP bit, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 14/23] arm/virt: enable PSCI emulation support for system emulation, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 11/23] target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers,
Peter Maydell <=
- [Qemu-devel] [PULL 12/23] target-arm: Add support for A32 and T32 HVC and SMC insns, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 08/23] target-arm: add powered off cpu state, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 09/23] target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 10/23] target-arm: add missing PSCI constants needed for PSCI emulation, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 07/23] omap_gpmc.c: Remove duplicate assignment, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 17/23] target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 18/23] target-arm: increase arrays of registers R13 & R14, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 20/23] target-arm: reject switching to monitor mode, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 13/23] target-arm: add emulation of PSCI calls for system emulation, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 05/23] arm_gic: remove unused parameter., Peter Maydell, 2014/10/24