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[Qemu-devel] [PULL 16/23] target-arm: Report a valid L1Ip field in CTR_E
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 16/23] target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any" |
Date: |
Fri, 24 Oct 2014 12:37:22 +0100 |
For the CPU type "any" (only used with linux-user) we were reporting
the L1Ip field as 0b00, which is reserved. Change this field to 0b10
instead, indicating a VIPT icache as the comment describes.
Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden
---
target-arm/cpu64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index a95367a..bb778b3d 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -151,7 +151,7 @@ static void aarch64_any_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
set_feature(&cpu->env, ARM_FEATURE_CRC);
- cpu->ctr = 0x80030003; /* 32 byte I and D cacheline size, VIPT icache */
+ cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
cpu->dcz_blocksize = 7; /* 512 bytes */
}
#endif
--
1.9.1
- [Qemu-devel] [PULL 00/23] target-arm queue, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 22/23] target-arm: make arm_current_el() return EL3, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 16/23] target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any",
Peter Maydell <=
- [Qemu-devel] [PULL 15/23] target-arm: Correct sense of the DCZID DZP bit, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 14/23] arm/virt: enable PSCI emulation support for system emulation, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 11/23] target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 12/23] target-arm: Add support for A32 and T32 HVC and SMC insns, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 08/23] target-arm: add powered off cpu state, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 09/23] target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 10/23] target-arm: add missing PSCI constants needed for PSCI emulation, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 07/23] omap_gpmc.c: Remove duplicate assignment, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 17/23] target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 18/23] target-arm: increase arrays of registers R13 & R14, Peter Maydell, 2014/10/24