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Re: [Qemu-devel] [PATCH 9/9] target-arm: A64: implement SVC, BRK
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 9/9] target-arm: A64: implement SVC, BRK |
Date: |
Mon, 09 Dec 2013 13:58:13 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 |
On 12/09/2013 10:12 AM, Peter Maydell wrote:
> + case 0:
> + /* SVC, HVC, SMC; since we don't support the Virtualization
> + * or TrustZone extensions these all UNDEF except SVC.
> + */
> + if (op2_ll != 1) {
> + unallocated_encoding(s);
> + break;
> + }
> + gen_exception_insn(s, 0, EXCP_SWI);
> + break;
Should the imm16 should be stored somewhere, for exception.syndrome?
I can only presume from this that the AA64 userland doesn't encode its syscall
number in the insn...
Otherwise,
Reviewed-by: Richard Henderson <address@hidden>
r~
- Re: [Qemu-devel] [PATCH 4/9] target-arm: A64: add support for ld/st with reg offset, (continued)
[Qemu-devel] [PATCH 8/9] target-arm: A64: add support for 3 src data proc insns, Peter Maydell, 2013/12/09
[Qemu-devel] [PATCH 6/9] target-arm: A64: add support for add, addi, sub, subi, Peter Maydell, 2013/12/09
[Qemu-devel] [PATCH 1/9] target-arm: A64: add support for stp (store pair), Peter Maydell, 2013/12/09
[Qemu-devel] [PATCH 9/9] target-arm: A64: implement SVC, BRK, Peter Maydell, 2013/12/09
- Re: [Qemu-devel] [PATCH 9/9] target-arm: A64: implement SVC, BRK,
Richard Henderson <=
Re: [Qemu-devel] [PATCH 0/9] target-arm: A64 decoder set 3: loads, stores, misc integer, Peter Maydell, 2013/12/09