[Qemu-devel] PCNet-PCI I/O ops byte order

[Oleksandr Tymoshenko]

Hello,

I'm working on QEMU/mips support for FreeBSD. qemu-system-mipsel works
just fine but I ran into a problem with qemu-system-mips. There are two 
devices on PCI bus in MALTA machine emulation. ATA IDE controller and
PCNet NIC:  hw/ide/pci.c and hw/net/pcnet-pci.c respectively. Problem is
I/O ops byte order for these two devices are defined inconsistently.
It's  DEVICE_LITTLE_ENDIAN for bmdma_addr_ioport_ops and 
DEVICE_NATIVE_ENDIAN for pcnet_io_ops. And since byte swapping
in my case performed by bus driver I can't get consistent behaviour
for these devices on big-endian system.

I don't have real hardware to run my code on but shouldn't all devices
on PCI bus treat words as little endian?

Thank you