[Qemu-devel] [RFC 06/14] tcg-aarch64: Handle zero as first argument to sub

[Richard Henderson]

In order to properly handle neg, as generated by TCG generic code.

Signed-off-by: Richard Henderson <address@hidden>
---
 tcg/aarch64/tcg-target.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 7aeb3cd..88bbfd2 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -110,6 +110,7 @@ static inline void patch_reloc(uint8_t *code_ptr, int type,
 #define TCG_CT_CONST_LI32 0x200
 #define TCG_CT_CONST_LI64 0x400
 #define TCG_CT_CONST_CMP  0x800
+#define TCG_CT_CONST_ZERO 0x1000
 
 #include "bitmask-table.h"
 
@@ -179,6 +180,9 @@ static int target_parse_constraint(TCGArgConstraint *ct,
     case 'L': /* logical immediate 64-bit */
         ct->ct |= TCG_CT_CONST_LI64;
         break;
+    case 'Z': /* zero */
+        ct->ct |= TCG_CT_CONST_ZERO;
+        break;
     default:
         return -1;
     }
@@ -208,6 +212,9 @@ static inline int tcg_target_const_match(tcg_target_long 
val,
     if ((ct & TCG_CT_CONST_CMP) && can_cmpi(val)) {
         return 1;
     }
+    if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
+        return 1;
+    }
 
     return 0;
 }
@@ -1218,6 +1225,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
        common code. It triggers the use of extended regs where appropriate. */
     AArch64Ext ext = E32;
 
+    /* Some operands are defined with "rZ" constraint, a register or
+       the zero register.  These need not actually test args[I] == 0.  */
+#define REG0(I)  (const_args[I] ? TCG_REG_XZR : args[I])
+
     switch (opc) {
     case INDEX_op_exit_tb:
         tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, args[0]);
@@ -1299,9 +1310,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         ext = E64; /* fall through */
     case INDEX_op_sub_i32:
         if (const_args[2]) {
-            tcg_out_addi(s, ext, args[0], args[1], -args[2]);
+            tcg_out_addi(s, ext, args[0], REG0(1), -args[2]);
         } else {
-            tcg_out_arith(s, INSN_SUB, ext, args[0], args[1], args[2], 0);
+            tcg_out_arith(s, INSN_SUB, ext, args[0], REG0(1), args[2], 0);
         }
         break;
 
@@ -1518,6 +1529,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
     default:
         tcg_abort(); /* opcode not implemented */
     }
+
+#undef REG0
 }
 
 static const TCGTargetOpDef aarch64_op_defs[] = {
@@ -1555,8 +1568,8 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
 
     { INDEX_op_add_i32, { "r", "r", "rA" } },
     { INDEX_op_add_i64, { "r", "r", "rA" } },
-    { INDEX_op_sub_i32, { "r", "r", "rA" } },
-    { INDEX_op_sub_i64, { "r", "r", "rA" } },
+    { INDEX_op_sub_i32, { "r", "rZ", "rA" } },
+    { INDEX_op_sub_i64, { "r", "rZ", "rA" } },
     { INDEX_op_mul_i32, { "r", "r", "r" } },
     { INDEX_op_mul_i64, { "r", "r", "r" } },
     { INDEX_op_and_i32, { "r", "r", "rK" } },
-- 
1.8.3.1