[Qemu-devel] [RFC 05/14] tcg-aarch64: Support andc, orc, eqv, not

[Richard Henderson]

Signed-off-by: Richard Henderson <address@hidden>
---
 tcg/aarch64/tcg-target.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
 tcg/aarch64/tcg-target.h | 16 ++++++++--------
 2 files changed, 52 insertions(+), 8 deletions(-)

diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 3640486..7aeb3cd 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -1314,6 +1314,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
             tcg_out_arith(s, INSN_AND, ext, args[0], args[1], args[2], 0);
         }
         break;
+    case INDEX_op_andc_i64:
+        ext = E64; /* fall through */
+    case INDEX_op_andc_i32:
+        if (const_args[2]) {
+            tcg_out_limm(s, INSN_ANDI, ext, args[0], args[1], ~args[2]);
+        } else {
+            tcg_out_arith(s, INSN_BIC, ext, args[0], args[1], args[2], 0);
+        }
+        break;
 
     case INDEX_op_or_i64:
         ext = E64; /* fall through */
@@ -1325,6 +1334,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         }
         break;
 
+    case INDEX_op_orc_i64:
+        ext = E64; /* fall through */
+    case INDEX_op_orc_i32:
+        if (const_args[2]) {
+            tcg_out_limm(s, INSN_ORRI, ext, args[0], args[1], ~args[2]);
+        } else {
+            tcg_out_arith(s, INSN_ORN, ext, args[0], args[1], args[2], 0);
+        }
+        break;
+
     case INDEX_op_xor_i64:
         ext = E64; /* fall through */
     case INDEX_op_xor_i32:
@@ -1335,6 +1354,22 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         }
         break;
 
+    case INDEX_op_eqv_i64:
+        ext = E64; /* fall through */
+    case INDEX_op_eqv_i32:
+        if (const_args[2]) {
+            tcg_out_limm(s, INSN_EORI, ext, args[0], args[1], ~args[2]);
+        } else {
+            tcg_out_arith(s, INSN_EON, ext, args[0], args[1], args[2], 0);
+        }
+        break;
+
+    case INDEX_op_not_i64:
+        ext = E64; /* fall through */
+    case INDEX_op_not_i32:
+        tcg_out_arith(s, INSN_ORN, ext, args[0], TCG_REG_XZR, args[1], 0);
+        break;
+
     case INDEX_op_mul_i64:
         ext = E64; /* fall through */
     case INDEX_op_mul_i32:
@@ -1530,6 +1565,15 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
     { INDEX_op_or_i64, { "r", "r", "rL" } },
     { INDEX_op_xor_i32, { "r", "r", "rK" } },
     { INDEX_op_xor_i64, { "r", "r", "rL" } },
+    { INDEX_op_andc_i32, { "r", "r", "rK" } },
+    { INDEX_op_andc_i64, { "r", "r", "rL" } },
+    { INDEX_op_orc_i32, { "r", "r", "rK" } },
+    { INDEX_op_orc_i64, { "r", "r", "rL" } },
+    { INDEX_op_eqv_i32, { "r", "r", "rK" } },
+    { INDEX_op_eqv_i64, { "r", "r", "rL" } },
+
+    { INDEX_op_not_i32, { "r", "r" } },
+    { INDEX_op_not_i64, { "r", "r" } },
 
     { INDEX_op_shl_i32, { "r", "r", "ri" } },
     { INDEX_op_shr_i32, { "r", "r", "ri" } },
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 51e5092..ffe9429 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -47,12 +47,12 @@ typedef enum {
 #define TCG_TARGET_HAS_ext16u_i32       1
 #define TCG_TARGET_HAS_bswap16_i32      1
 #define TCG_TARGET_HAS_bswap32_i32      1
-#define TCG_TARGET_HAS_not_i32          0
+#define TCG_TARGET_HAS_not_i32          1
 #define TCG_TARGET_HAS_neg_i32          0
 #define TCG_TARGET_HAS_rot_i32          1
-#define TCG_TARGET_HAS_andc_i32         0
-#define TCG_TARGET_HAS_orc_i32          0
-#define TCG_TARGET_HAS_eqv_i32          0
+#define TCG_TARGET_HAS_andc_i32         1
+#define TCG_TARGET_HAS_orc_i32          1
+#define TCG_TARGET_HAS_eqv_i32          1
 #define TCG_TARGET_HAS_nand_i32         0
 #define TCG_TARGET_HAS_nor_i32          0
 #define TCG_TARGET_HAS_deposit_i32      0
@@ -73,12 +73,12 @@ typedef enum {
 #define TCG_TARGET_HAS_bswap16_i64      1
 #define TCG_TARGET_HAS_bswap32_i64      1
 #define TCG_TARGET_HAS_bswap64_i64      1
-#define TCG_TARGET_HAS_not_i64          0
+#define TCG_TARGET_HAS_not_i64          1
 #define TCG_TARGET_HAS_neg_i64          0
 #define TCG_TARGET_HAS_rot_i64          1
-#define TCG_TARGET_HAS_andc_i64         0
-#define TCG_TARGET_HAS_orc_i64          0
-#define TCG_TARGET_HAS_eqv_i64          0
+#define TCG_TARGET_HAS_andc_i64         1
+#define TCG_TARGET_HAS_orc_i64          1
+#define TCG_TARGET_HAS_eqv_i64          1
 #define TCG_TARGET_HAS_nand_i64         0
 #define TCG_TARGET_HAS_nor_i64          0
 #define TCG_TARGET_HAS_deposit_i64      0
-- 
1.8.3.1