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Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC
From: |
Benjamin Herrenschmidt |
Subject: |
Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC |
Date: |
Thu, 29 Sep 2011 06:58:44 +1000 |
On Wed, 2011-09-28 at 16:26 +0200, Alexander Graf wrote:
>
> This makes sure that when device emulation overwrites code that is
> already present in the cache of a CPU, it gets flushed from the
> icache. I'm fairly sure we want that :). But let's ask Ben and David
> as well.
Hrm we don't need that. DMA doesn't flush the icache on power. The
kernel will take care of it if necessary.
The only case you do need it is when doing the initial load of the
kernel or SLOF image before you execute it.
Cheers,
Ben.
- [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC, Jan Kiszka, 2011/09/28
- Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC, Alexander Graf, 2011/09/28
- Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC, Jan Kiszka, 2011/09/28
- Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC, Scott Wood, 2011/09/28
- Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC, Benjamin Herrenschmidt, 2011/09/28
- Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC, Scott Wood, 2011/09/28
- Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC, Benjamin Herrenschmidt, 2011/09/28
Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC,
Benjamin Herrenschmidt <=