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Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC
From: |
Alexander Graf |
Subject: |
Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC |
Date: |
Wed, 28 Sep 2011 16:26:05 +0200 |
On 28.09.2011, at 16:23, Jan Kiszka wrote:
> Alex,
>
> we have this diff in qemu-kvm:
>
> diff --git a/exec.c b/exec.c
> index c1e045d..f188549 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -3950,6 +3955,11 @@ void cpu_physical_memory_rw(target_phys_addr_t addr,
> uint8_t *buf,
> cpu_physical_memory_set_dirty_flags(
> addr1, (0xff & ~CODE_DIRTY_FLAG));
> }
> + /* qemu doesn't execute guest code directly, but kvm does
> + therefore flush instruction caches */
> + if (kvm_enabled())
> + flush_icache_range((unsigned long)ptr,
> + ((unsigned long)ptr)+l);
> qemu_put_ram_ptr(ptr);
> }
> } else {
>
>
> flush_icache_range() is doing something only on PPC hosts. So do we need
> this upstream?
This makes sure that when device emulation overwrites code that is already
present in the cache of a CPU, it gets flushed from the icache. I'm fairly sure
we want that :). But let's ask Ben and David as well.
Alex
- [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC, Jan Kiszka, 2011/09/28
- Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC,
Alexander Graf <=
- Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC, Jan Kiszka, 2011/09/28
- Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC, Scott Wood, 2011/09/28
- Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC, Benjamin Herrenschmidt, 2011/09/28
- Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC, Scott Wood, 2011/09/28
- Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC, Benjamin Herrenschmidt, 2011/09/28
Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC, Benjamin Herrenschmidt, 2011/09/28