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[Qemu-devel] [PATCH v4 13/32] target-xtensa: mark reserved and TBD opcod
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From: |
Max Filippov |
|
Subject: |
[Qemu-devel] [PATCH v4 13/32] target-xtensa: mark reserved and TBD opcodes |
|
Date: |
Fri, 2 Sep 2011 00:45:41 +0400 |
Reserved opcodes must generate illegal instruction exception. Usually
they signal emulation quality problems.
Not implemented opcodes are good to see.
Signed-off-by: Max Filippov <address@hidden>
---
target-xtensa/translate.c | 110 ++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 109 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index e37d75c..e6d749f 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -267,6 +267,14 @@ static void disas_xtensa_insn(DisasContext *dc)
} \
} while (0)
+#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
+#define RESERVED() do { \
+ qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
+ dc->pc, _b0, _b1, _b2, __FILE__, __LINE__); \
+ goto invalid_opcode; \
+ } while (0)
+
+
#ifdef TARGET_WORDS_BIGENDIAN
#define OP0 (((_b0) & 0xf0) >> 4)
#define OP1 (((_b2) & 0xf0) >> 4)
@@ -367,9 +375,11 @@ static void disas_xtensa_insn(DisasContext *dc)
case 0: /*SNM0*/
switch (CALLX_M) {
case 0: /*ILL*/
+ TBD();
break;
case 1: /*reserved*/
+ RESERVED();
break;
case 2: /*JR*/
@@ -381,9 +391,11 @@ static void disas_xtensa_insn(DisasContext *dc)
case 1: /*RETWw*/
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
+ TBD();
break;
case 3: /*reserved*/
+ RESERVED();
break;
}
break;
@@ -404,6 +416,7 @@ static void disas_xtensa_insn(DisasContext *dc)
case 2: /*CALLX8w*/
case 3: /*CALLX12w*/
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
+ TBD();
break;
}
break;
@@ -412,12 +425,59 @@ static void disas_xtensa_insn(DisasContext *dc)
case 1: /*MOVSPw*/
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
+ TBD();
break;
case 2: /*SYNC*/
+ TBD();
+ break;
+
+ case 3: /*RFEIx*/
+ TBD();
+ break;
+
+ case 4: /*BREAKx*/
+ HAS_OPTION(XTENSA_OPTION_EXCEPTION);
+ TBD();
+ break;
+
+ case 5: /*SYSCALLx*/
+ HAS_OPTION(XTENSA_OPTION_EXCEPTION);
+ TBD();
+ break;
+
+ case 6: /*RSILx*/
+ HAS_OPTION(XTENSA_OPTION_INTERRUPT);
+ TBD();
+ break;
+
+ case 7: /*WAITIx*/
+ HAS_OPTION(XTENSA_OPTION_INTERRUPT);
+ TBD();
+ break;
+
+ case 8: /*ANY4p*/
+ HAS_OPTION(XTENSA_OPTION_BOOLEAN);
+ TBD();
+ break;
+
+ case 9: /*ALL4p*/
+ HAS_OPTION(XTENSA_OPTION_BOOLEAN);
+ TBD();
break;
- case 3:
+ case 10: /*ANY8p*/
+ HAS_OPTION(XTENSA_OPTION_BOOLEAN);
+ TBD();
+ break;
+
+ case 11: /*ALL8p*/
+ HAS_OPTION(XTENSA_OPTION_BOOLEAN);
+ TBD();
+ break;
+
+ default: /*reserved*/
+ RESERVED();
break;
}
@@ -473,13 +533,16 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 6: /*RER*/
+ TBD();
break;
case 7: /*WER*/
+ TBD();
break;
case 8: /*ROTWw*/
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
+ TBD();
break;
case 14: /*NSAu*/
@@ -493,11 +556,13 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
default: /*reserved*/
+ RESERVED();
break;
}
break;
case 5: /*TLB*/
+ TBD();
break;
case 6: /*RT0*/
@@ -518,11 +583,13 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
default: /*reserved*/
+ RESERVED();
break;
}
break;
case 7: /*reserved*/
+ RESERVED();
break;
case 8: /*ADD*/
@@ -582,6 +649,9 @@ static void disas_xtensa_insn(DisasContext *dc)
gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
gen_wsr(dc, RSR_SR, tmp);
tcg_temp_free(tmp);
+ if (!sregnames[RSR_SR]) {
+ TBD();
+ }
}
break;
@@ -671,21 +741,29 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
default: /*reserved*/
+ RESERVED();
break;
}
break;
case 2: /*RST2*/
+ TBD();
break;
case 3: /*RST3*/
switch (OP2) {
case 0: /*RSR*/
gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
+ if (!sregnames[RSR_SR]) {
+ TBD();
+ }
break;
case 1: /*WSR*/
gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
+ if (!sregnames[RSR_SR]) {
+ TBD();
+ }
break;
case 2: /*SEXTu*/
@@ -778,10 +856,12 @@ static void disas_xtensa_insn(DisasContext *dc)
case 12: /*MOVFp*/
HAS_OPTION(XTENSA_OPTION_BOOLEAN);
+ TBD();
break;
case 13: /*MOVTp*/
HAS_OPTION(XTENSA_OPTION_BOOLEAN);
+ TBD();
break;
case 14: /*RUR*/
@@ -791,6 +871,7 @@ static void disas_xtensa_insn(DisasContext *dc)
tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
} else {
qemu_log("RUR %d not implemented, ", st);
+ TBD();
}
}
break;
@@ -801,6 +882,7 @@ static void disas_xtensa_insn(DisasContext *dc)
tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]);
} else {
qemu_log("WUR %d not implemented, ", RSR_SR);
+ TBD();
}
}
break;
@@ -822,27 +904,34 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 6: /*CUST0*/
+ RESERVED();
break;
case 7: /*CUST1*/
+ RESERVED();
break;
case 8: /*LSCXp*/
HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
+ TBD();
break;
case 9: /*LSC4*/
+ TBD();
break;
case 10: /*FP0*/
HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
+ TBD();
break;
case 11: /*FP1*/
HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
+ TBD();
break;
default: /*reserved*/
+ RESERVED();
break;
}
break;
@@ -894,6 +983,7 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 7: /*CACHEc*/
+ TBD();
break;
case 9: /*L16SI*/
@@ -946,6 +1036,7 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
default: /*reserved*/
+ RESERVED();
break;
}
break;
@@ -953,10 +1044,12 @@ static void disas_xtensa_insn(DisasContext *dc)
case 3: /*LSCIp*/
HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
+ TBD();
break;
case 4: /*MAC16d*/
HAS_OPTION(XTENSA_OPTION_MAC16);
+ TBD();
break;
case 5: /*CALLN*/
@@ -970,6 +1063,7 @@ static void disas_xtensa_insn(DisasContext *dc)
case 2: /*CALL8w*/
case 3: /*CALL12w*/
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
+ TBD();
break;
}
break;
@@ -1012,28 +1106,35 @@ static void disas_xtensa_insn(DisasContext *dc)
switch (BRI8_M) {
case 0: /*ENTRYw*/
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
+ TBD();
break;
case 1: /*B1*/
switch (BRI8_R) {
case 0: /*BFp*/
HAS_OPTION(XTENSA_OPTION_BOOLEAN);
+ TBD();
break;
case 1: /*BTp*/
HAS_OPTION(XTENSA_OPTION_BOOLEAN);
+ TBD();
break;
case 8: /*LOOP*/
+ TBD();
break;
case 9: /*LOOPNEZ*/
+ TBD();
break;
case 10: /*LOOPGTZ*/
+ TBD();
break;
default: /*reserved*/
+ RESERVED();
break;
}
@@ -1169,28 +1270,35 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 1: /*RETW.Nn*/
+ HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
+ TBD();
break;
case 2: /*BREAK.Nn*/
+ TBD();
break;
case 3: /*NOP.Nn*/
break;
case 6: /*ILL.Nn*/
+ TBD();
break;
default: /*reserved*/
+ RESERVED();
break;
}
break;
default: /*reserved*/
+ RESERVED();
break;
}
break;
default: /*reserved*/
+ RESERVED();
break;
}
--
1.7.6
- Re: [Qemu-devel] [PATCH v4 09/32] target-xtensa: add special and user registers, (continued)
- [Qemu-devel] [PATCH v4 01/32] target-xtensa: add target stubs, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 10/32] target-xtensa: implement RST3 group, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 12/32] target-xtensa: implement LSAI group, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 14/32] target-xtensa: implement SYNC group, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 15/32] target-xtensa: implement CACHE group, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 11/32] target-xtensa: implement shifts (ST1 and RST1 groups), Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 26/32] target-xtensa: implement CPENABLE and PRID SRs, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 16/32] target-xtensa: add PS register and access control, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 13/32] target-xtensa: mark reserved and TBD opcodes,
Max Filippov <=
- [Qemu-devel] [PATCH v4 22/32] target-xtensa: implement unaligned exception option, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 18/32] target-xtensa: implement RST2 group (32 bit mul/div/rem), Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 31/32] MAINTAINERS: add xtensa maintainer, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 21/32] target-xtensa: implement extended L32R, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 23/32] target-xtensa: implement SIMCALL, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 19/32] target-xtensa: implement windowed registers, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 27/32] target-xtensa: implement relocatable vectors, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 17/32] target-xtensa: implement exceptions, Max Filippov, 2011/09/01