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[Qemu-devel] [PATCH v4 26/32] target-xtensa: implement CPENABLE and PRID
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH v4 26/32] target-xtensa: implement CPENABLE and PRID SRs |
Date: |
Fri, 2 Sep 2011 00:45:54 +0400 |
Signed-off-by: Max Filippov <address@hidden>
---
hw/xtensa_sample.c | 1 +
target-xtensa/cpu.h | 2 ++
target-xtensa/translate.c | 7 +++++++
3 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/hw/xtensa_sample.c b/hw/xtensa_sample.c
index 9f7733b..c2ad48a 100644
--- a/hw/xtensa_sample.c
+++ b/hw/xtensa_sample.c
@@ -51,6 +51,7 @@ static void xtensa_init(ram_addr_t ram_size,
exit(1);
}
qemu_register_reset(xtensa_sample_reset, env);
+ env->sregs[PRID] = n;
}
ram_offset = qemu_ram_alloc(NULL, "xtensa.dram", 0x10000);
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 474466c..37f8b7f 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -118,12 +118,14 @@ enum {
DEPC = 192,
EPS2 = 194,
EXCSAVE1 = 209,
+ CPENABLE = 224,
INTSET = 226,
INTCLEAR = 227,
INTENABLE = 228,
PS = 230,
EXCCAUSE = 232,
CCOUNT = 234,
+ PRID = 235,
EXCVADDR = 238,
CCOMPARE = 240,
};
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 2b95a13..423cbae 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -101,12 +101,14 @@ static const char * const sregnames[256] = {
[EXCSAVE1 + 4] = "EXCSAVE5",
[EXCSAVE1 + 5] = "EXCSAVE6",
[EXCSAVE1 + 6] = "EXCSAVE7",
+ [CPENABLE] = "CPENABLE",
[INTSET] = "INTSET",
[INTCLEAR] = "INTCLEAR",
[INTENABLE] = "INTENABLE",
[PS] = "PS",
[EXCCAUSE] = "EXCCAUSE",
[CCOUNT] = "CCOUNT",
+ [PRID] = "PRID",
[EXCVADDR] = "EXCVADDR",
[CCOMPARE] = "CCOMPARE0",
[CCOMPARE + 1] = "CCOMPARE1",
@@ -476,6 +478,10 @@ static void gen_wsr_ps(DisasContext *dc, uint32_t sr,
TCGv_i32 v)
gen_jumpi_check_loop_end(dc, -1);
}
+static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+{
+}
+
static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
uint32_t id = sr - CCOMPARE;
@@ -502,6 +508,7 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32
s)
[INTCLEAR] = gen_wsr_intclear,
[INTENABLE] = gen_wsr_intenable,
[PS] = gen_wsr_ps,
+ [PRID] = gen_wsr_prid,
[CCOMPARE] = gen_wsr_ccompare,
[CCOMPARE + 1] = gen_wsr_ccompare,
[CCOMPARE + 2] = gen_wsr_ccompare,
--
1.7.6
- [Qemu-devel] [PATCH v4 08/32] target-xtensa: implement JX/RET0/CALLX, (continued)
- [Qemu-devel] [PATCH v4 08/32] target-xtensa: implement JX/RET0/CALLX, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 09/32] target-xtensa: add special and user registers, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 01/32] target-xtensa: add target stubs, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 10/32] target-xtensa: implement RST3 group, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 12/32] target-xtensa: implement LSAI group, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 14/32] target-xtensa: implement SYNC group, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 15/32] target-xtensa: implement CACHE group, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 11/32] target-xtensa: implement shifts (ST1 and RST1 groups), Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 26/32] target-xtensa: implement CPENABLE and PRID SRs,
Max Filippov <=
- [Qemu-devel] [PATCH v4 16/32] target-xtensa: add PS register and access control, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 13/32] target-xtensa: mark reserved and TBD opcodes, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 22/32] target-xtensa: implement unaligned exception option, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 18/32] target-xtensa: implement RST2 group (32 bit mul/div/rem), Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 31/32] MAINTAINERS: add xtensa maintainer, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 21/32] target-xtensa: implement extended L32R, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 23/32] target-xtensa: implement SIMCALL, Max Filippov, 2011/09/01
- [Qemu-devel] [PATCH v4 19/32] target-xtensa: implement windowed registers, Max Filippov, 2011/09/01