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[Qemu-commits] [qemu/qemu] 4d5738: tcg/ppc: implement rem[u]_i{32, 64} w

From: Richard Henderson
Subject: [Qemu-commits] [qemu/qemu] 4d5738: tcg/ppc: implement rem[u]_i{32, 64} with mod[su][wd]
Date: Tue, 21 Jun 2022 13:48:25 -0700 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 4d5738222ff0a7f4d56fd4a2971b0605726a8fb2
      
https://github.com/qemu/qemu/commit/4d5738222ff0a7f4d56fd4a2971b0605726a8fb2
  Author: Matheus Kowalczuk Ferst <matheus.ferst@eldorado.org.br>
  Date:   2022-06-20 (Mon, 20 Jun 2022)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc
    M tcg/ppc/tcg-target.h

  Log Message:
  -----------
  tcg/ppc: implement rem[u]_i{32,64} with mod[su][wd]

Power ISA v3.0 introduced mod[su][wd] insns that can be used to
implement rem[u]_i{32,64}.

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: adb5974dcc5ee7fe122c74fb85d3bae331101ec3
      
https://github.com/qemu/qemu/commit/adb5974dcc5ee7fe122c74fb85d3bae331101ec3
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2022-06-20 (Mon, 20 Jun 2022)

  Changed paths:
    M target/avr/cpu.c
    M target/avr/cpu.h
    M target/avr/helper.c

  Log Message:
  -----------
  target/avr: Drop avr_cpu_memory_rw_debug()

CPUClass::memory_rw_debug() holds a callback for GDB memory access.
If not provided, cpu_memory_rw_debug() is used by the GDB stub.
Drop avr_cpu_memory_rw_debug() which does nothing special.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220322095004.70682-1-bmeng.cn@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a82fd5a4ec24d923ff1e6da128c0fd4a74079d99
      
https://github.com/qemu/qemu/commit/a82fd5a4ec24d923ff1e6da128c0fd4a74079d99
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2022-06-20 (Mon, 20 Jun 2022)

  Changed paths:
    M accel/tcg/tcg-accel-ops-mttcg.c
    M accel/tcg/tcg-accel-ops-rr.c

  Log Message:
  -----------
  accel/tcg: Init TCG cflags in vCPU thread handler

Move TCG cflags initialization to thread handler.
Remove the duplicated assert checks.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220323171751.78612-6-philippe.mathieu.daude@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 18b8c47f8e66c1c45a0fb59cfd6ed4dfeb25c6f6
      
https://github.com/qemu/qemu/commit/18b8c47f8e66c1c45a0fb59cfd6ed4dfeb25c6f6
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2022-06-20 (Mon, 20 Jun 2022)

  Changed paths:
    M accel/tcg/tcg-accel-ops.c

  Log Message:
  -----------
  accel/tcg: Reorganize tcg_accel_ops_init()

Reorg TCG AccelOpsClass initialization to emphasis icount
mode share more code with single-threaded TCG.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220323171751.78612-7-philippe.mathieu.daude@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3f42906c9ab2c777a895b48b87b8107167e4a275
      
https://github.com/qemu/qemu/commit/3f42906c9ab2c777a895b48b87b8107167e4a275
  Author: Idan Horowitz <idan.horowitz@gmail.com>
  Date:   2022-06-21 (Tue, 21 Jun 2022)

  Changed paths:
    M util/qemu-timer.c

  Log Message:
  -----------
  qemu-timer: Skip empty timer lists before locking in 
qemu_clock_deadline_ns_all

This decreases qemu_clock_deadline_ns_all's share from 23.2% to 13% in a
profile of icount-enabled aarch64-softmmu.

Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220114004358.299534-2-idan.horowitz@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 418ade7849ce7641c0f7333718caf5091a02fd4c
      
https://github.com/qemu/qemu/commit/418ade7849ce7641c0f7333718caf5091a02fd4c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-21 (Tue, 21 Jun 2022)

  Changed paths:
    M softmmu/physmem.c

  Log Message:
  -----------
  softmmu: Always initialize xlat in address_space_translate_for_iotlb

The bug is an uninitialized memory read, along the translate_fail
path, which results in garbage being read from iotlb_to_section,
which can lead to a crash in io_readx/io_writex.

The bug may be fixed by writing any value with zero
in ~TARGET_PAGE_MASK, so that the call to iotlb_to_section using
the xlat'ed address returns io_mem_unassigned, as desired by the
translate_fail path.

It is most useful to record the original physical page address,
which will eventually be logged by memory_region_access_valid
when the access is rejected by unassigned_mem_accepts.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1065
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220621153829.366423-1-richard.henderson@linaro.org>


  Commit: 79713752870c7d730d128b9158edb0c58b82fcf9
      
https://github.com/qemu/qemu/commit/79713752870c7d730d128b9158edb0c58b82fcf9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-21 (Tue, 21 Jun 2022)

  Changed paths:
    M util/cacheflush.c
    R util/cacheinfo.c
    M util/meson.build

  Log Message:
  -----------
  util: Merge cacheflush.c and cacheinfo.c

Combine the two files into cacheflush.c.  There's a couple of bits
that would be helpful to share between the two, and combining them
seems better than exporting the bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220621014837.189139-2-richard.henderson@linaro.org>


  Commit: bdd50dc7d09c90525b80da4f056b849049893732
      
https://github.com/qemu/qemu/commit/bdd50dc7d09c90525b80da4f056b849049893732
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-21 (Tue, 21 Jun 2022)

  Changed paths:
    M util/cacheflush.c

  Log Message:
  -----------
  util/cacheflush: Merge aarch64 ctr_el0 usage

Merge init_ctr_el0 into arch_cache_info.  In flush_idcache_range,
use the pre-computed line sizes from the global variables.
Use CONFIG_DARWIN in preference to __APPLE__.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220621014837.189139-3-richard.henderson@linaro.org>


  Commit: c79a8e840c435bc26a251e34b043318e8b2081db
      
https://github.com/qemu/qemu/commit/c79a8e840c435bc26a251e34b043318e8b2081db
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2022-06-21 (Tue, 21 Jun 2022)

  Changed paths:
    M util/cacheflush.c

  Log Message:
  -----------
  util/cacheflush: Optimize flushing when ppc host has coherent icache

On linux, the AT_HWCAP bit PPC_FEATURE_ICACHE_SNOOP indicates
that we can use a simplified 3 instruction flush sequence.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20220519141131.29839-1-npiggin@gmail.com>
[rth: update after merging cacheflush.c and cacheinfo.c]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220621014837.189139-4-richard.henderson@linaro.org>


  Commit: f200ff158d5abcb974a6b597a962b6b2fbea2b06
      
https://github.com/qemu/qemu/commit/f200ff158d5abcb974a6b597a962b6b2fbea2b06
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-21 (Tue, 21 Jun 2022)

  Changed paths:
    M accel/tcg/tcg-accel-ops-mttcg.c
    M accel/tcg/tcg-accel-ops-rr.c
    M accel/tcg/tcg-accel-ops.c
    M softmmu/physmem.c
    M target/avr/cpu.c
    M target/avr/cpu.h
    M target/avr/helper.c
    M tcg/ppc/tcg-target.c.inc
    M tcg/ppc/tcg-target.h
    M util/cacheflush.c
    R util/cacheinfo.c
    M util/meson.build
    M util/qemu-timer.c

  Log Message:
  -----------
  Merge tag 'pull-tcg-20220621' of https://gitlab.com/rth7680/qemu into staging

Speed empty timer list in qemu_clock_deadline_ns_all.
Implement remainder for Power3.1 hosts.
Optimize ppc host icache flushing.
Cleanups to tcg_accel_ops_init.
Fix mmio crash accessing unmapped physical memory.

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# gpg: Signature made Tue 21 Jun 2022 01:45:31 PM PDT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
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# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[ultimate]

* tag 'pull-tcg-20220621' of https://gitlab.com/rth7680/qemu:
  util/cacheflush: Optimize flushing when ppc host has coherent icache
  util/cacheflush: Merge aarch64 ctr_el0 usage
  util: Merge cacheflush.c and cacheinfo.c
  softmmu: Always initialize xlat in address_space_translate_for_iotlb
  qemu-timer: Skip empty timer lists before locking in 
qemu_clock_deadline_ns_all
  accel/tcg: Reorganize tcg_accel_ops_init()
  accel/tcg: Init TCG cflags in vCPU thread handler
  target/avr: Drop avr_cpu_memory_rw_debug()
  tcg/ppc: implement rem[u]_i{32,64} with mod[su][wd]

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/5cdcfd861e3c...f200ff158d5a
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