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[Qemu-commits] [qemu/qemu] 61f302: target/ppc: Implemented vector divide
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 61f302: target/ppc: Implemented vector divide instructions |
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Date: |
Tue, 21 Jun 2022 11:22:01 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 61f302615aaf94937e664b76f8e35f8896e73b07
https://github.com/qemu/qemu/commit/61f302615aaf94937e664b76f8e35f8896e73b07
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-06-20 (Mon, 20 Jun 2022)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Implemented vector divide instructions
Implement the following PowerISA v3.1 instructions:
vdivsw: Vector Divide Signed Word
vdivuw: Vector Divide Unsigned Word
vdivsd: Vector Divide Signed Doubleword
vdivud: Vector Divide Unsigned Doubleword
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220525134954.85056-2-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 1700f2bf9744602d008035cc69075e158690fcd9
https://github.com/qemu/qemu/commit/1700f2bf9744602d008035cc69075e158690fcd9
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-06-20 (Mon, 20 Jun 2022)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Implemented vector divide quadword
Implement the following PowerISA v3.1 instructions:
vdivsq: Vector Divide Signed Quadword
vdivuq: Vector Divide Unsigned Quadword
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220525134954.85056-3-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 9a1f0866a3caf0f98ff588ba84da4fa6be2dc39c
https://github.com/qemu/qemu/commit/9a1f0866a3caf0f98ff588ba84da4fa6be2dc39c
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-06-20 (Mon, 20 Jun 2022)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Implemented vector divide extended word
Implement the following PowerISA v3.1 instructions:
vdivesw: Vector Divide Extended Signed Word
vdiveuw: Vector Divide Extended Unsigned Word
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220525134954.85056-4-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 4724bbd28475210d25e0c949a7f424550487b187
https://github.com/qemu/qemu/commit/4724bbd28475210d25e0c949a7f424550487b187
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-06-20 (Mon, 20 Jun 2022)
Changed paths:
M include/qemu/host-utils.h
M include/qemu/int128.h
M util/host-utils.c
Log Message:
-----------
host-utils: Implemented unsigned 256-by-128 division
Based on already existing QEMU implementation, created an unsigned 256
bit by 128 bit division needed to implement the vector divide extended
unsigned instruction from PowerISA3.1
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220525134954.85056-5-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 62c9947fb769235cc11fe6af18dc9620fbbeafc2
https://github.com/qemu/qemu/commit/62c9947fb769235cc11fe6af18dc9620fbbeafc2
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-06-20 (Mon, 20 Jun 2022)
Changed paths:
M include/qemu/host-utils.h
M util/host-utils.c
Log Message:
-----------
host-utils: Implemented signed 256-by-128 division
Based on already existing QEMU implementation created a signed
256 bit by 128 bit division needed to implement the vector divide
extended signed quadword instruction from PowerISA 3.1
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220525134954.85056-6-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: a173ba88be2b3e6aaae969629ee8a2577df2adc9
https://github.com/qemu/qemu/commit/a173ba88be2b3e6aaae969629ee8a2577df2adc9
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-06-20 (Mon, 20 Jun 2022)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Implemented remaining vector divide extended
Implement the following PowerISA v3.1 instructions:
vdivesd: Vector Divide Extended Signed Doubleword
vdiveud: Vector Divide Extended Unsigned Doubleword
vdivesq: Vector Divide Extended Signed Quadword
vdiveuq: Vector Divide Extended Unsigned Quadword
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220525134954.85056-7-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 5adb27cd8faac8a3b3e8dc44328348d0e3c85aaf
https://github.com/qemu/qemu/commit/5adb27cd8faac8a3b3e8dc44328348d0e3c85aaf
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-06-20 (Mon, 20 Jun 2022)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Implemented vector module word/doubleword
Implement the following PowerISA v3.1 instructions:
vmodsw: Vector Modulo Signed Word
vmoduw: Vector Modulo Unsigned Word
vmodsd: Vector Modulo Signed Doubleword
vmodud: Vector Modulo Unsigned Doubleword
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220525134954.85056-8-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: b80bec3a0706402521f64353f87f5e8fea709057
https://github.com/qemu/qemu/commit/b80bec3a0706402521f64353f87f5e8fea709057
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-06-20 (Mon, 20 Jun 2022)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Implemented vector module quadword
Implement the following PowerISA v3.1 instructions:
vmodsq: Vector Modulo Signed Quadword
vmoduq: Vector Modulo Unsigned Quadword
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/744
Message-Id: <20220525134954.85056-9-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 453eb94c7651e791c3cbc1bbf8880677a61342ca
https://github.com/qemu/qemu/commit/453eb94c7651e791c3cbc1bbf8880677a61342ca
Author: Michael S. Tsirkin <mst@redhat.com>
Date: 2022-06-20 (Mon, 20 Jun 2022)
Changed paths:
M hw/ppc/ppc440_uc.c
Log Message:
-----------
ppc: fix boot with sam460ex
Recent changes to pcie_host corrected size of its internal region to
match what it expects: only the low 28 bits are ever decoded. Previous
code just ignored bit 29 (if size was 1 << 29) in the address which does
not make much sense. We are now asserting on size > 1 << 28 instead,
but PPC 4xx actually allows guest to configure different sizes, and some
firmwares seem to set it to 1 << 29.
This caused e.g. qemu-system-ppc -M sam460ex to exit with an assert when
the guest writes a value to CFGMSK register when trying to map config
space. This is done in the board firmware in ppc4xx_init_pcie_port() in
roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
It's not clear what the proper fix should be but for now let's force the
size to 256MB, so anything outside the expected address range is
ignored.
Fixes: commit 1f1a7b2269 ("include/hw/pci/pcie_host: Correct
PCIE_MMCFG_SIZE_MAX")
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220526224229.95183-1-mst@redhat.com>
[danielhb: changed commit msg as BALATON Zoltan suggested]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 8f7d41e0c9cdcb696df564100e77c81ef6a9d026
https://github.com/qemu/qemu/commit/8f7d41e0c9cdcb696df564100e77c81ef6a9d026
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-06-20 (Mon, 20 Jun 2022)
Changed paths:
M target/ppc/int_helper.c
Log Message:
-----------
target/ppc: fix vbpermd in big endian hosts
The extract64 arguments are not endian dependent as they are only used
for bitwise operations. The current behavior in little-endian hosts is
correct; since the indexes in VRB are in PowerISA-ordering, we should
always invert the value before calling extract64. Also, using the VsrD
macro, we can have a single EXTRACT_BIT definition for big and
little-endian with the correct behavior.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220601125355.1266165-1-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 151308677c977dae5fdb5c62f20722ddd25aeef9
https://github.com/qemu/qemu/commit/151308677c977dae5fdb5c62f20722ddd25aeef9
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2022-06-20 (Mon, 20 Jun 2022)
Changed paths:
M hw/intc/pnv_xive2.c
Log Message:
-----------
pnv/xive2: Access direct mapped thread contexts from all chips
When accessing a thread context through the IC BAR, the offset of the
page in the BAR identifies the CPU. From that offset, we can compute
the PIR (processor ID register) of the CPU to do the data structure
lookup. On P10, the current code assumes an access for node 0 when
computing the PIR. Everything is almost in place to allow access for
other nodes though. So this patch reworks how the PIR value is
computed so that we can access all thread contexts through the IC BAR.
The PIR is already correct on P9, so no need to modify anything there.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220602165310.558810-1-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 78d6b5d33a1d0fcf485ecba684f03c13527800e4
https://github.com/qemu/qemu/commit/78d6b5d33a1d0fcf485ecba684f03c13527800e4
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-06-20 (Mon, 20 Jun 2022)
Changed paths:
M hw/pci-host/pnv_phb3.c
M hw/pci-host/pnv_phb4.c
M hw/pci-host/pnv_phb4_pec.c
Log Message:
-----------
ppc/pnv: fix extra indent spaces with DEFINE_PROP*
The DEFINE_PROP* macros in pnv files are using extra spaces for no good
reason.
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20220602215351.149910-1-danielhb413@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: feeef6b6dd971be34e6e608c90238f65c935d846
https://github.com/qemu/qemu/commit/feeef6b6dd971be34e6e608c90238f65c935d846
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-06-20 (Mon, 20 Jun 2022)
Changed paths:
M target/ppc/int_helper.c
Log Message:
-----------
target/ppc: avoid int32 multiply overflow in int_helper.c
Coverity is not thrilled about the multiply operations being done in
ger_rank8() and ger_rank2(), giving an error like the following:
Integer handling issues (OVERFLOW_BEFORE_WIDEN)
Potentially overflowing expression "sextract32(a, 4 * i, 4) *
sextract32(b, 4 * i, 4)" with type "int" (32 bits, signed) is evaluated
using 32-bit arithmetic, and then used in a context that expects an
expression of type "int64_t" (64 bits, signed).
Fix both instances where this occur by adding an int64_t cast in the
first operand, forcing the result to be 64 bit.
Fixes: Coverity CID 1489444, 1489443
Fixes: 345531533f26 ("target/ppc: Implemented xvi*ger* instructions")
Cc: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Cc: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Message-Id: <20220602141449.118173-1-danielhb413@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 5980167e07bb691a36ef002a00f9e8b993f0800e
https://github.com/qemu/qemu/commit/5980167e07bb691a36ef002a00f9e8b993f0800e
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-06-20 (Mon, 20 Jun 2022)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: fix unreachable code in fpu_helper.c
Commit c29018cc7395 added an env->fpscr OR operation using a ternary
that checks if 'error' is not zero:
env->fpscr |= error ? FP_FEX : 0;
However, in the current body of do_fpscr_check_status(), 'error' is
granted to be always non-zero at that point. The result is that Coverity
is less than pleased:
Control flow issues (DEADCODE)
Execution cannot reach the expression "0ULL" inside this statement:
"env->fpscr |= (error ? 1073...".
Remove the ternary and always make env->fpscr |= FP_FEX.
Cc: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Cc: Richard Henderson <richard.henderson@linaro.org>
Fixes: Coverity CID 1489442
Fixes: c29018cc7395 ("target/ppc: Implemented xvf*ger*")
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Message-Id: <20220602191048.137511-1-danielhb413@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 609b1c866925049f22a79623021076192f7a6595
https://github.com/qemu/qemu/commit/609b1c866925049f22a79623021076192f7a6595
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2022-06-20 (Mon, 20 Jun 2022)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: cpu_init: Clean up stop state on cpu reset
The 'resume_as_sreset' attribute of a cpu is set when a thread is
entering a stop state on ppc books. It causes the thread to be
re-routed to vector 0x100 when woken up by an exception. So it must be
cleared on reset or a thread might be re-routed unexpectedly after a
reset, when it was not in a stop state and/or when the appropriate
exception handler isn't set up yet.
Using skiboot, it can be tested by resetting the system when it is
quiet and most threads are idle and in stop state.
After the reset occurs, skiboot elects a primary thread and all the
others wait in secondary_wait. The primary thread does all the system
initialization from main_cpu_entry() and at some point, the
decrementer interrupt starts ticking. The exception vector for the
decrementer interrupt is in place, so that shouldn't be a
problem. However, if that primary thread was in stop state prior to
the reset, and because the resume_as_sreset parameters is still set,
it is re-routed to exception vector 0x100. Which, at that time, is
still defined as the entry point for BML. So that primary thread
restarts as new and ends up being treated like any other secondary
thread. All threads are now waiting in secondary_wait.
It results in a full system hang with no message on the console, as
the uart hasn't been init'ed yet. It's actually not obvious to realise
what's happening if not tracing reset (-d cpu_reset). The fix is
simply to clear the 'resume_as_sreset' attribute on reset.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220617095222.612212-1-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 5cdcfd861e3cdb98d3239ba78c97a1a2b13d2a70
https://github.com/qemu/qemu/commit/5cdcfd861e3cdb98d3239ba78c97a1a2b13d2a70
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-21 (Tue, 21 Jun 2022)
Changed paths:
M hw/intc/pnv_xive2.c
M hw/pci-host/pnv_phb3.c
M hw/pci-host/pnv_phb4.c
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/ppc440_uc.c
M include/qemu/host-utils.h
M include/qemu/int128.h
M target/ppc/cpu_init.c
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.c.inc
M util/host-utils.c
Log Message:
-----------
Merge tag 'pull-ppc-20220621' of https://gitlab.com/danielhb/qemu into staging
ppc patch queue for 2022-06-21:
- tcg and target/ppc: vector divide instructions and a vbpermd fix for
BE hosts
- ppc440_uc.c: fix boot of sam460ex machine
- target/ppc: fix stop state on cpu reset
- xive2: Access direct mapped thread contexts from all chips
- a couple of Coverity fixes
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# gpg: Signature made Tue 21 Jun 2022 02:41:00 AM PDT
# gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
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* tag 'pull-ppc-20220621' of https://gitlab.com/danielhb/qemu:
target/ppc: cpu_init: Clean up stop state on cpu reset
target/ppc: fix unreachable code in fpu_helper.c
target/ppc: avoid int32 multiply overflow in int_helper.c
ppc/pnv: fix extra indent spaces with DEFINE_PROP*
pnv/xive2: Access direct mapped thread contexts from all chips
target/ppc: fix vbpermd in big endian hosts
ppc: fix boot with sam460ex
target/ppc: Implemented vector module quadword
target/ppc: Implemented vector module word/doubleword
target/ppc: Implemented remaining vector divide extended
host-utils: Implemented signed 256-by-128 division
host-utils: Implemented unsigned 256-by-128 division
target/ppc: Implemented vector divide extended word
target/ppc: Implemented vector divide quadword
target/ppc: Implemented vector divide instructions
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/c8b2d413761a...5cdcfd861e3c