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[Qemu-commits] [qemu/qemu] e955ac: MAINTAINERS: Add MIPS general archite

From: Richard Henderson
Subject: [Qemu-commits] [qemu/qemu] e955ac: MAINTAINERS: Add MIPS general architecture support...
Date: Tue, 02 Nov 2021 12:17:40 -0700 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: e955acd91dc3c1dfe13e09d2b63242932d54ae14
      
https://github.com/qemu/qemu/commit/e955acd91dc3c1dfe13e09d2b63242932d54ae14
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add MIPS general architecture support entry

The architecture is covered in TCG (frontend and backend)
and hardware models. Add a generic section matching the
'mips' word in patch subjects.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211004092515.3819836-2-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6cee54794dc8d27f5cf4a7fac3d7b8e3146988d3
      
https://github.com/qemu/qemu/commit/6cee54794dc8d27f5cf4a7fac3d7b8e3146988d3
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware

MIPS CPS and GIC models are unrelated to the TCG frontend.
Move them as new sections under the 'Devices' group.

Cc: Paul Burton <paulburton@kernel.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211027041416.1237433-3-f4bug@amsat.org>


  Commit: f44d1d4ed9feb50f4d791b0b6827c1e0dba20555
      
https://github.com/qemu/qemu/commit/f44d1d4ed9feb50f4d791b0b6827c1e0dba20555
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Split MIPS TCG frontend vs MIPS machines/hardware

Hardware emulated models don't belong to the TCG MAINTAINERS
section. Move them to a new 'Overall MIPS Machines' section
in the 'MIPS Machines' group.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211004092515.3819836-4-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 06df015b69ba2812a9cff6858d32491d6a7b9c44
      
https://github.com/qemu/qemu/commit/06df015b69ba2812a9cff6858d32491d6a7b9c44
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa_helper.c

  Log Message:
  -----------
  target/mips: Fix MSA MADDV.B opcode

The result of the 'Vector Multiply and Add' opcode is incorrect
with Byte vectors. Probably due to a copy/paste error, commit
7a7a162adde mistakenly used the $wt (target register) instead
of $wd (destination register) as first operand. Fix that.

Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Fixes: 7a7a162adde ("target/mips: msa: Split helpers for MADDV.<B|H|W|D>")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-2-f4bug@amsat.org>


  Commit: 36b39a69b2e7649d317a08dd81da39a7c9bc14f3
      
https://github.com/qemu/qemu/commit/36b39a69b2e7649d317a08dd81da39a7c9bc14f3
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa_helper.c

  Log Message:
  -----------
  target/mips: Fix MSA MSUBV.B opcode

The result of the 'Vector Multiply and Subtract' opcode is
incorrect with Byte vectors. Probably due to a copy/paste error,
commit 5f148a02327 mistakenly used the $wt (target register)
instead  of $wd (destination register) as first operand. Fix that.

Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Fixes: 5f148a02327 ("target/mips: msa: Split helpers for MSUBV.<B|H|W|D>")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-3-f4bug@amsat.org>


  Commit: bbc213b37c1366cf64701d37a21b709c97714a2d
      
https://github.com/qemu/qemu/commit/bbc213b37c1366cf64701d37a21b709c97714a2d
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Adjust style in msa_translate_init()

While the first 'off' variable assignment is unused, it helps
to better understand the code logic. Move the assignation where
it would have been used so it is easier to compare the MSA
registers based on FPU ones versus the MSA specific registers.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211023214803.522078-34-f4bug@amsat.org>


  Commit: 40f75c02d4c796cb54826b65edd2e2530e5129f8
      
https://github.com/qemu/qemu/commit/40f75c02d4c796cb54826b65edd2e2530e5129f8
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Use dup_const() to simplify

The dup_const() helper makes the code easier to follow, use it.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211028210843.2120802-5-f4bug@amsat.org>


  Commit: 340ee8b3f1872c7f8969a5eb48fc3b5a9284e27b
      
https://github.com/qemu/qemu/commit/340ee8b3f1872c7f8969a5eb48fc3b5a9284e27b
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Have check_msa_access() return a boolean

Have check_msa_access() return a boolean value so we can
return early if MSA is not enabled (the instruction got
decoded properly, but we raised an exception).

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-6-f4bug@amsat.org>


  Commit: 7e9db46d645dca27f28ec28e0fc479778e410d5f
      
https://github.com/qemu/qemu/commit/7e9db46d645dca27f28ec28e0fc479778e410d5f
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Use enum definitions from CPUMIPSMSADataFormat enum

Replace magic DataFormat value by the corresponding
enum from CPUMIPSMSADataFormat.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-7-f4bug@amsat.org>


  Commit: d61566cf78d97952ecf6a00a64b168c61fadd4ce
      
https://github.com/qemu/qemu/commit/d61566cf78d97952ecf6a00a64b168c61fadd4ce
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v

This 'shift amount' format is not always 16-bit, so name it
generically as 'sa'. This will help to unify the various
arg_msa decodetree generated structures.

Rename the @bz format -> @bz_v (specific @bz with df=3) and
@bz_df -> @bz (generic @bz).

Since we modify &msa_bz, re-align its arguments, so the other
structures added in the following commits stay visually aligned.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-8-f4bug@amsat.org>


  Commit: 75094c334e4c2f6d4646274cd73006d8931a31de
      
https://github.com/qemu/qemu/commit/75094c334e4c2f6d4646274cd73006d8931a31de
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA LDI opcode to decodetree

Convert the LDI opcode (Immediate Load) to decodetree. Since it
overlaps with the generic MSA handler, use a decodetree overlap
group.

Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-9-f4bug@amsat.org>


  Commit: b8e74816ec8ee7efdce6aa290cd18c937b317133
      
https://github.com/qemu/qemu/commit/b8e74816ec8ee7efdce6aa290cd18c937b317133
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA I5 instruction format to decodetree

Convert instructions with a 5-bit immediate value to decodetree.

Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-10-f4bug@amsat.org>


  Commit: 4701d23aef1d096da20b46ce817e30f81bd01b4b
      
https://github.com/qemu/qemu/commit/4701d23aef1d096da20b46ce817e30f81bd01b4b
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA BIT instruction format to decodetree

Convert instructions with an immediate bit index and
data format df/m to decodetree.

Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211028210843.2120802-11-f4bug@amsat.org>


  Commit: a9e17958330a971c379ed99f349158b269b4e4c2
      
https://github.com/qemu/qemu/commit/a9e17958330a971c379ed99f349158b269b4e4c2
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA SHF opcode to decodetree

Convert the SHF opcode (Immediate Set Shuffle Elements) to decodetree.

Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-12-f4bug@amsat.org>


  Commit: 7cc351ff9dc033d31ea45c72fc4b708ef585577d
      
https://github.com/qemu/qemu/commit/7cc351ff9dc033d31ea45c72fc4b708ef585577d
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA I8 instruction format to decodetree

Convert instructions with an 8-bit immediate value and either
implicit data format or data format df to decodetree.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-13-f4bug@amsat.org>


  Commit: ce121fe23443fbf885b3c0a583a91efd2efa6e10
      
https://github.com/qemu/qemu/commit/ce121fe23443fbf885b3c0a583a91efd2efa6e10
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA load/store instruction format to decodetree

Convert load/store instructions to decodetree.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-14-f4bug@amsat.org>


  Commit: 5c5b64000c751ed3f3535c17095161fea02db660
      
https://github.com/qemu/qemu/commit/5c5b64000c751ed3f3535c17095161fea02db660
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA 2RF instruction format to decodetree

Convert 2-register floating-point operations to decodetree.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-15-f4bug@amsat.org>


  Commit: 675bf34a6fe9db202edd49755c8c586764f5eabf
      
https://github.com/qemu/qemu/commit/675bf34a6fe9db202edd49755c8c586764f5eabf
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA FILL opcode to decodetree

Convert the FILL opcode (Vector Fill from GPR) to decodetree.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-16-f4bug@amsat.org>


  Commit: adcff99a6b41c029841aee30582606e6ae196507
      
https://github.com/qemu/qemu/commit/adcff99a6b41c029841aee30582606e6ae196507
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA 2R instruction format to decodetree

Convert 2-register operations to decodetree.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-17-f4bug@amsat.org>


  Commit: 7acb5c78a75421851b778b463c88c232ce1dc184
      
https://github.com/qemu/qemu/commit/7acb5c78a75421851b778b463c88c232ce1dc184
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA VEC instruction format to decodetree

Convert 3-register instructions with implicit data formats
to decodetree.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-18-f4bug@amsat.org>


  Commit: ff29e5d3c0ac7f88b9cf1840451f5fc6c958171d
      
https://github.com/qemu/qemu/commit/ff29e5d3c0ac7f88b9cf1840451f5fc6c958171d
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)

Convert 3-register floating-point or fixed-point operations
to decodetree.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211028210843.2120802-19-f4bug@amsat.org>


  Commit: 2d5246f30573c27cee609021850fdd3c56cda1ec
      
https://github.com/qemu/qemu/commit/2d5246f30573c27cee609021850fdd3c56cda1ec
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)

Convert 3-register floating-point or fixed-point operations
to decodetree.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-20-f4bug@amsat.org>


  Commit: 67bedef51aa1144975c619f8559848819cdc309a
      
https://github.com/qemu/qemu/commit/67bedef51aa1144975c619f8559848819cdc309a
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)

Convert 3-register operations to decodetree.

Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.

Note, the format definition could be named @3rf_b (for
3R with a df field BYTE-based) but since the instruction
class is named '3R', we simply call the format @3r to
ease reviewing the msa.decode file.
However we directly call the trans_msa_3rf() function,
which handles the BYTE-based df field.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-21-f4bug@amsat.org>


  Commit: f18708a53adc0549526fbeba5d1e892c0c4bf49c
      
https://github.com/qemu/qemu/commit/f18708a53adc0549526fbeba5d1e892c0c4bf49c
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)

Convert 3-register operations to decodetree.

Per the Encoding of Operation Field for 3R Instruction Format'
(Table 3.25), these instructions are not defined for the BYTE
format. Therefore the TRANS_DF_iii_b() macro returns 'false'
in that case, because no such instruction is decoded.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211028210843.2120802-22-f4bug@amsat.org>


  Commit: c79db8c239fb4272de3cd0741c0ecfd549d5588a
      
https://github.com/qemu/qemu/commit/c79db8c239fb4272de3cd0741c0ecfd549d5588a
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)

Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit
Insert Right) opcodes to decodetree.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-23-f4bug@amsat.org>


  Commit: 0a086d2e80d3214b56f672d2f976525e46f1b476
      
https://github.com/qemu/qemu/commit/0a086d2e80d3214b56f672d2f976525e46f1b476
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)

Convert 3-register operations to decodetree.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-24-f4bug@amsat.org>


  Commit: 0a510c934c36f6314508ad4e7b5fd6ca8eb02c06
      
https://github.com/qemu/qemu/commit/0a510c934c36f6314508ad4e7b5fd6ca8eb02c06
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA ELM instruction format to decodetree

Convert instructions with an immediate element index
and data format df/n to decodetree.

Since the 'data format' and 'n' fields are constant values,
use tcg_constant_i32() instead of a TCG temporaries.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-25-f4bug@amsat.org>


  Commit: 2f2745c81a3c196fc149fcf243b11cae13fd126b
      
https://github.com/qemu/qemu/commit/2f2745c81a3c196fc149fcf243b11cae13fd126b
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA COPY_U opcode to decodetree

Convert the COPY_U opcode (Element Copy to GPR Unsigned) to
decodetree.

Since the 'n' field is a constant value, use tcg_constant_i32()
instead of a TCG temporary.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211028210843.2120802-26-f4bug@amsat.org>


  Commit: 97fe675519d3e7406dfed2fe8cc7af9cdbec3cec
      
https://github.com/qemu/qemu/commit/97fe675519d3e7406dfed2fe8cc7af9cdbec3cec
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree

Convert the COPY_S (Element Copy to GPR Signed) opcode
and INSERT (GPR Insert Element) opcode to decodetree.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-27-f4bug@amsat.org>


  Commit: 62ba0e855a0ffe90142de9b6aac0e89ab8c0b894
      
https://github.com/qemu/qemu/commit/62ba0e855a0ffe90142de9b6aac0e89ab8c0b894
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert MSA MOVE.V opcode to decodetree

Convert the MOVE.V opcode (Vector Move) to decodetree.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-28-f4bug@amsat.org>


  Commit: 6f74237691461fb2f875aecb35a92a073d0bb7fb
      
https://github.com/qemu/qemu/commit/6f74237691461fb2f875aecb35a92a073d0bb7fb
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert CFCMSA opcode to decodetree

Convert the CFCMSA (Copy From Control MSA register) opcode
to decodetree. Since it overlaps with the SPLATI opcode,
use a decodetree overlap group.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-29-f4bug@amsat.org>


  Commit: 643ec9022e72bb9100c6455de3d81cab8eed0a50
      
https://github.com/qemu/qemu/commit/643ec9022e72bb9100c6455de3d81cab8eed0a50
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Convert CTCMSA opcode to decodetree

Convert the CTCMSA (Copy To Control MSA register) opcode
to decodetree. Since it overlaps with the SLDI opcode,
use a decodetree overlap group.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-30-f4bug@amsat.org>


  Commit: 75d12c8c249c1791e4b24bfea0fba14d2ccd64ac
      
https://github.com/qemu/qemu/commit/75d12c8c249c1791e4b24bfea0fba14d2ccd64ac
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Remove generic MSA opcode

All opcodes have been converted to decodetree. The generic
MSA handler is now pointless, remove it.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-31-f4bug@amsat.org>


  Commit: 73053f62287256cb69e95f43fa424eb4342d6935
      
https://github.com/qemu/qemu/commit/73053f62287256cb69e95f43fa424eb4342d6935
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/tcg/msa.decode

  Log Message:
  -----------
  target/mips: Remove one MSA unnecessary decodetree overlap group

Only the MSA generic opcode was overlapping with the other
instructions. Since the previous commit removed it, we can
now remove the overlap group. The decodetree script forces
us to re-indent the opcodes.

Diff trivial to review using `git-diff --ignore-all-space`.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-32-f4bug@amsat.org>


  Commit: ba7b6f025ba84a5a32c6cd07ffc8634ad2b33c20
      
https://github.com/qemu/qemu/commit/ba7b6f025ba84a5a32c6cd07ffc8634ad2b33c20
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/cpu-defs.c.inc

  Log Message:
  -----------
  target/mips: Fix Loongson-3A4000 MSAIR config register

When using the Loongson-3A4000 CPU, the MSAIR is returned with a
zero value (because unimplemented). Checking on real hardware,
this value appears incorrect:

  $ cat /proc/cpuinfo
  system type     : generic-loongson-machine
  machine         : loongson,generic
  cpu model       : Loongson-3 V0.4  FPU V0.1
  model name      : Loongson-3A R4 (Loongson-3A4000) @ 1800MHz
  isa             : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 
mips64r2
  ASEs implemented        : vz msa loongson-mmi loongson-cam loongson-ext 
loongson-ext2
  ...

Checking the CFCMSA opcode result with gdb we get 0x60140:

  Breakpoint 1, 0x00000001200037c4 in main ()
  1: x/i $pc
  => 0x1200037c4 <main+52>:  cfcmsa       v0,msa_ir
  (gdb) si
  0x00000001200037c8 in main ()
  (gdb) i r v0
  v0: 0x60140

MSAIR bits 17 and 18 are "reserved" per the spec revision 1.12,
so mask them out, and set MSAIR=0x0140 for the Loongson-3A4000
CPU model added in commit af868995e1b.

Cc: Huacai Chen <chenhuacai@kernel.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211026180920.1085516-1-f4bug@amsat.org>


  Commit: 675cf7817c9c0171af387faf8169bd5b8bd3d303
      
https://github.com/qemu/qemu/commit/675cf7817c9c0171af387faf8169bd5b8bd3d303
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M target/mips/cpu-defs.c.inc

  Log Message:
  -----------
  target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU

FCR0_HAS2008 flag has been enabled in commit ba5c79f2622
("target-mips: indicate presence of IEEE 754-2008 FPU in
R6/R5+MSA CPUs"), so remove the obsolete FIXME comment.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211028212103.2126176-1-f4bug@amsat.org>


  Commit: d3647ef1fdaf4dcaecb794b525e9def1e5d81245
      
https://github.com/qemu/qemu/commit/d3647ef1fdaf4dcaecb794b525e9def1e5d81245
  Author: BALATON Zoltan <balaton@eik.bme.hu>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M hw/usb/hcd-uhci.c

  Log Message:
  -----------
  usb/uhci: Misc clean up

Fix a comment for coding style so subsequent patch will not get
checkpatch error and simplify and shorten uhci_update_irq().

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: 
<b68a57dfcf181e73272b4dc951f8cc6e76b0d182.1635161629.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: ece29df33b8e0e35760c4f76b0cf7b1af928b0b4
      
https://github.com/qemu/qemu/commit/ece29df33b8e0e35760c4f76b0cf7b1af928b0b4
  Author: BALATON Zoltan <balaton@eik.bme.hu>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M hw/usb/hcd-uhci.c
    M hw/usb/hcd-uhci.h
    M hw/usb/vt82c686-uhci-pci.c

  Log Message:
  -----------
  usb/uhci: Disallow user creating a vt82c686-uhci-pci device

Because this device only works as part of VIA superio chips set user
creatable to false. Since the class init method is common for UHCI
variants introduce a flag in UHCIInfo for this.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: 
<e6abf1f19ca72bbc2d8a5a6aa941edbf87a9845f.1635161629.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: e4f5b93986cdcc137487ebea6e84b9d9e82e0990
      
https://github.com/qemu/qemu/commit/e4f5b93986cdcc137487ebea6e84b9d9e82e0990
  Author: BALATON Zoltan <balaton@eik.bme.hu>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M hw/usb/hcd-uhci.c
    M hw/usb/hcd-uhci.h

  Log Message:
  -----------
  usb/uhci: Replace pci_set_irq with qemu_set_irq

Instead of using pci_set_irq, store the irq in the device state and
use it explicitly so variants having different interrupt handling can
use their own.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: 
<b39066e03c8731f4197d50bc79b403f797599999.1635161629.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 4f3b0a4d757f40cbd51987e4c7cf7cbd10951178
      
https://github.com/qemu/qemu/commit/4f3b0a4d757f40cbd51987e4c7cf7cbd10951178
  Author: BALATON Zoltan <balaton@eik.bme.hu>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M hw/usb/vt82c686-uhci-pci.c

  Log Message:
  -----------
  hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts

This device is part of a superio/ISA bridge chip and IRQs from it are
routed to an ISA interrupt set by the Interrupt Line PCI config
register. Implement this in a vt82c686-uhci-pci specific irq handler
Using via_isa_set_irq().

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: 
<8d7ed385e33a847d8ddc669163a68b5ca57f82ce.1635161629.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 6f08c9c5316a80a049d4861eaac5844466ba3eba
      
https://github.com/qemu/qemu/commit/6f08c9c5316a80a049d4861eaac5844466ba3eba
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too"

Per the "P32 Porting Guide" (rev 1.2) [1], chapter 2:

  p32 ABI Overview
  ----------------

  The Application Binary Interface, or ABI, is the set of rules
  that all binaries must follow in order to run on a nanoMIPS
  system. This includes, for example, object file format,
  instruction set, data layout, subroutine calling convention,
  and system call numbers. The ABI is one part of the mechanism
  that maintains binary compatibility across all nanoMIPS platforms.

  p32 improves on o32 to provide an ABI that is efficient in both
  code density and performance. p32 is required for the nanoMIPS
  architecture.

So far QEMU only support the MIPS o32 / n32 / n64 ABIs. The p32 ABI
is not implemented, therefore we can not run any nanoMIPS binary.

Revert commit f72541f3a59 ("elf: Relax MIPS' elf_check_arch() to
accept EM_NANOMIPS too").

See also the "ELF ABI Supplement" [2].

[1] 
http://codescape.mips.com/components/toolchain/nanomips/2019.03-01/docs/MIPS_nanoMIPS_p32_ABI_Porting_Guide_01_02_DN00184.pdf
[2] 
http://codescape.mips.com/components/toolchain/nanomips/2019.03-01/docs/MIPS_nanoMIPS_ABI_supplement_01_03_DN00179.pdf

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211101114800.2692157-1-f4bug@amsat.org>


  Commit: 157f75435e08447c50c1f52df73d1222491f6303
      
https://github.com/qemu/qemu/commit/157f75435e08447c50c1f52df73d1222491f6303
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M MAINTAINERS
    M hw/usb/hcd-uhci.c
    M hw/usb/hcd-uhci.h
    M hw/usb/vt82c686-uhci-pci.c
    M linux-user/elfload.c
    M target/mips/cpu-defs.c.inc
    M target/mips/tcg/msa.decode
    M target/mips/tcg/msa_helper.c
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/philmd/tags/mips-20211102' into staging

MIPS patches queue

- Fine-grained MAINTAINERS sections
- Fix MSA MADDV.B / MSUBV.B opcodes
- Convert MSA opcodes to decodetree
- Correct Loongson-3A4000 MSAIR register
- Do not accept ELF nanoMIPS binaries on linux-user
- Use ISA instead of PCI interrupts in VT82C686 PCI device

# gpg: Signature made Tue 02 Nov 2021 09:41:04 AM EDT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" 
[full]

* remotes/philmd/tags/mips-20211102: (41 commits)
  Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too"
  hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts
  usb/uhci: Replace pci_set_irq with qemu_set_irq
  usb/uhci: Disallow user creating a vt82c686-uhci-pci device
  usb/uhci: Misc clean up
  target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU
  target/mips: Fix Loongson-3A4000 MSAIR config register
  target/mips: Remove one MSA unnecessary decodetree overlap group
  target/mips: Remove generic MSA opcode
  target/mips: Convert CTCMSA opcode to decodetree
  target/mips: Convert CFCMSA opcode to decodetree
  target/mips: Convert MSA MOVE.V opcode to decodetree
  target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
  target/mips: Convert MSA COPY_U opcode to decodetree
  target/mips: Convert MSA ELM instruction format to decodetree
  target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)
  target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)
  target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
  target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
  target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/102f39b32dd3...157f75435e08
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