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[Qemu-commits] [qemu/qemu] b2b111: hw/display/tc6393xb: Remove dead code
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] b2b111: hw/display/tc6393xb: Remove dead code for handling... |
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Date: |
Sat, 06 Mar 2021 05:52:07 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: b2b111faec50918a5e3b78942be5b81cb46a51fc
https://github.com/qemu/qemu/commit/b2b111faec50918a5e3b78942be5b81cb46a51fc
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-05 (Fri, 05 Mar 2021)
Changed paths:
M hw/display/tc6393xb.c
Log Message:
-----------
hw/display/tc6393xb: Remove dead code for handling non-32bpp surfaces
For a long time now the UI layer has guaranteed that the console
surface is always 32 bits per pixel RGB. Remove the legacy dead
code from the tc6393xb display device which was handling the
possibility that the console surface was some other format.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215103215.4944-3-peter.maydell@linaro.org
Commit: 8cfd41dd89981c49aa15c603c3e3233580620d72
https://github.com/qemu/qemu/commit/8cfd41dd89981c49aa15c603c3e3233580620d72
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/display/tc6393xb_template.h
Log Message:
-----------
hw/display/tc6393xb: Expand out macros in template header
Now the template header is included only for BITS==32, expand
out all the macros that depended on the BITS setting.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215103215.4944-4-peter.maydell@linaro.org
Commit: 0dc51b002482d4b5e60f634dcbcd8a3a906d7b97
https://github.com/qemu/qemu/commit/0dc51b002482d4b5e60f634dcbcd8a3a906d7b97
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/display/tc6393xb.c
R hw/display/tc6393xb_template.h
Log Message:
-----------
hw/display/tc6393xb: Inline tc6393xb_draw_graphic32() at its callsite
The function tc6393xb_draw_graphic32() is called in exactly one place,
so just inline the function body at its callsite. This allows us to
drop the template header entirely.
The code move includes a single added space after 'for' to fix
the coding style.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210215103215.4944-5-peter.maydell@linaro.org
Commit: 52b8ac590daebe1bbdaa2a5757ba5e05a626fab5
https://github.com/qemu/qemu/commit/52b8ac590daebe1bbdaa2a5757ba5e05a626fab5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/display/omap_lcd_template.h
Log Message:
-----------
hw/display/omap_lcdc: Expand out macros in template header
The omap_lcdc template header is already only included once, for
DEPTH==32, but it still has all the macro-driven parameterization
for other depths. Expand out all the macros in the header.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210215103215.4944-6-peter.maydell@linaro.org
Commit: 78b40bfb8fee5bb8ecff176522ad8098476cab5d
https://github.com/qemu/qemu/commit/78b40bfb8fee5bb8ecff176522ad8098476cab5d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/display/omap_lcd_template.h
Log Message:
-----------
hw/display/omap_lcdc: Drop broken bigendian ifdef
The draw_line16_32() function in the omap_lcdc template header
includes an ifdef for the case where HOST_WORDS_BIGENDIAN matches
TARGET_WORDS_BIGENDIAN. This is trying to optimise for "source
bitmap and destination bitmap format match", but it is broken,
because in this function the formats don't match: the source is
16-bit colour and the destination is 32-bit colour, so a memcpy()
will produce corrupted graphics output. Drop the bogus ifdef.
This bug was introduced in commit ea644cf343129, when we dropped
support for DEPTH values other than 32 from the template header.
The old #if line was
#if DEPTH == 16 && defined(HOST_WORDS_BIGENDIAN) ==
defined(TARGET_WORDS_BIGENDIAN)
and this was mistakenly changed to
#if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
rather than deleting the #if as now having an always-false condition.
Fixes: ea644cf343129
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210215103215.4944-7-peter.maydell@linaro.org
Commit: 0c6d9ff0afa3500af875d64382c2a6ca9d7934a0
https://github.com/qemu/qemu/commit/0c6d9ff0afa3500af875d64382c2a6ca9d7934a0
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/display/omap_lcd_template.h
Log Message:
-----------
hw/display/omap_lcdc: Fix coding style issues in template header
Fix some minor coding style issues in the template header,
so checkpatch doesn't complain when we move the code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210215103215.4944-8-peter.maydell@linaro.org
Commit: 1cccdd1807d17939d2d28df00d9040eea5c357db
https://github.com/qemu/qemu/commit/1cccdd1807d17939d2d28df00d9040eea5c357db
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
R hw/display/omap_lcd_template.h
M hw/display/omap_lcdc.c
Log Message:
-----------
hw/display/omap_lcdc: Inline template header into C file
We only include the template header once, so just inline it into the
source file for the device.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210215103215.4944-9-peter.maydell@linaro.org
Commit: cfb08215ca3b8df4662e08328f91d43c2603f4b2
https://github.com/qemu/qemu/commit/cfb08215ca3b8df4662e08328f91d43c2603f4b2
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/display/omap_lcdc.c
Log Message:
-----------
hw/display/omap_lcdc: Delete unnecessary macro
The macro draw_line_func is used only once; just expand it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210215103215.4944-10-peter.maydell@linaro.org
Commit: 7713fff47d31e7607e52c9247fb7b628ed6bb096
https://github.com/qemu/qemu/commit/7713fff47d31e7607e52c9247fb7b628ed6bb096
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/display/tcx.c
Log Message:
-----------
hw/display/tcx: Drop unnecessary code for handling BGR format outputs
For a long time now the UI layer has guaranteed that the console
surface is always 32 bits per pixel, RGB. The TCX code already
assumes 32bpp, but it still has some checks of is_surface_bgr()
in an attempt to support 32bpp BGR. is_surface_bgr() will always
return false for the qemu_console_surface(), unless the display
device itself has deliberately created an alternate-format
surface via a function like qemu_create_displaysurface_from().
Drop the never-used BGR-handling code, and assert that we have
a 32-bit surface rather than just doing nothing if it isn't.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215102149.20513-1-peter.maydell@linaro.org
Commit: a3e24690b8f7724e7acf9eeb83613302dc907747
https://github.com/qemu/qemu/commit/a3e24690b8f7724e7acf9eeb83613302dc907747
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Make SYSCLK frequency board-specific
The AN524 has a different SYSCLK frequency from the AN505 and AN521;
make the SYSCLK frequency a field in the MPS2TZMachineClass rather
than a compile-time constant so we can support the AN524.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-2-peter.maydell@linaro.org
Commit: 4fb013afcc037c27e3d0cd9af437a737106cca00
https://github.com/qemu/qemu/commit/4fb013afcc037c27e3d0cd9af437a737106cca00
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
M hw/arm/mps2.c
M hw/misc/mps2-scc.c
M include/hw/misc/mps2-scc.h
Log Message:
-----------
hw/misc/mps2-scc: Support configurable number of OSCCLK values
Currently the MPS2 SCC device implements a fixed number of OSCCLK
values (3). The variant of this device in the MPS3 AN524 board has 6
OSCCLK values. Switch to using a PROP_ARRAY, which allows board code
to specify how large the OSCCLK array should be as well as its
values.
With a variable-length property array, the SCC no longer specifies
default values for the OSCCLKs, so we must set them explicitly in the
board code. This defaults are actually incorrect for the an521 and
an505; we will correct this bug in a following patch.
This is a migration compatibility break for all the mps boards.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-3-peter.maydell@linaro.org
Commit: 9f9107e887a048d386ed94e52c1e22cbe4f58a4d
https://github.com/qemu/qemu/commit/9f9107e887a048d386ed94e52c1e22cbe4f58a4d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511
We were previously using the default OSCCLK settings, which are
correct for the older MPS2 boards (mps2-an385, mps2-an386,
mps2-an500, mps2-an511), but wrong for the mps2-an505 and mps2-511
implemented in mps2-tz.c. Now we're setting the values explicitly we
can fix them to be correct.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-4-peter.maydell@linaro.org
Commit: f7c71b21f27b9cbac2c30eda11a93eb7f8722161
https://github.com/qemu/qemu/commit/f7c71b21f27b9cbac2c30eda11a93eb7f8722161
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board
The AN505 and AN511 happen to share the same OSCCLK values, but the
AN524 will have a different set (and more of them), so split the
settings out to be per-board.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-5-peter.maydell@linaro.org
Commit: e8556f435eee97d508b58c06c156990d537823ab
https://github.com/qemu/qemu/commit/e8556f435eee97d508b58c06c156990d537823ab
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/misc/mps2-fpgaio.c
M include/hw/misc/mps2-fpgaio.h
Log Message:
-----------
hw/misc/mps2-fpgaio: Make number of LEDs configurable by board
The MPS2 board has 2 LEDs, but the MPS3 board has 10 LEDs. The
FPGAIO device is similar on both sets of boards, but the LED0
register has correspondingly more bits that have an effect. Add a
device property for number of LEDs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-6-peter.maydell@linaro.org
Commit: b2234223fd511230e933bba2572928ca97028bb8
https://github.com/qemu/qemu/commit/b2234223fd511230e933bba2572928ca97028bb8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/misc/mps2-fpgaio.c
M include/hw/misc/mps2-fpgaio.h
Log Message:
-----------
hw/misc/mps2-fpgaio: Support SWITCH register
MPS3 boards have an extra SWITCH register in the FPGAIO block which
reports the value of some switches. Implement this, governed by a
property the board code can use to specify whether whether it exists.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-7-peter.maydell@linaro.org
Commit: de77e8f4d2eec3c0ec9a74ad0da63cd9faec6aa7
https://github.com/qemu/qemu/commit/de77e8f4d2eec3c0ec9a74ad0da63cd9faec6aa7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board
Set the FPGAIO num-leds and have-switches properties explicitly
per-board, rather than relying on the defaults. The AN505 and AN521
both have the same settings as the default values, but the AN524 will
be different.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-8-peter.maydell@linaro.org
Commit: ba94ffd7d18b4724733819eaef3953617d4e81ab
https://github.com/qemu/qemu/commit/ba94ffd7d18b4724733819eaef3953617d4e81ab
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type
In the mps2-tz board code, we handle devices whose interrupt lines
must be wired to all CPUs by creating IRQ splitter devices for the
AN521, because it has 2 CPUs, but wiring the device IRQ directly to
the SSE/IoTKit input for the AN505, which has only 1 CPU.
We can avoid making an explicit check on the board type constant by
instead creating and using the IRQ splitters for any board with more
than 1 CPU. This avoids having to add extra cases to the
conditionals every time we add new boards.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-9-peter.maydell@linaro.org
Commit: 11e1d41265c3915c5fa4c4bc2457bcad2fe1da74
https://github.com/qemu/qemu/commit/11e1d41265c3915c5fa4c4bc2457bcad2fe1da74
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Make number of IRQs board-specific
The AN524 has more interrupt lines than the AN505 and AN521; make
numirq board-specific rather than a compile-time constant.
Since the difference is small (92 on the current boards and 95 on the
new one) we don't dynamically allocate the cpu_irq_splitter[] array
but leave it as a fixed length array whose size is the maximum needed
for any of the boards.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-10-peter.maydell@linaro.org
Commit: 8e4b4c1ca6a9d46ddc727d9485e1ae2e98226aca
https://github.com/qemu/qemu/commit/8e4b4c1ca6a9d46ddc727d9485e1ae2e98226aca
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/misc/mps2-scc.c
M include/hw/misc/mps2-scc.h
Log Message:
-----------
hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524
The AN524 version of the SCC interface has different behaviour for
some of the CFG registers; implement it.
Each board in this family can have minor differences in the meaning
of the CFG registers, so rather than trying to specify all the
possible semantics via individual device properties, we make the
behaviour conditional on the part-number field of the SCC_ID register
which the board code already passes us.
For the AN524, the differences are:
* CFG3 is reserved rather than being board switches
* CFG5 is a new register ("ACLK Frequency in Hz")
* CFG6 is a new register ("Clock divider for BRAM")
We implement both of the new registers as reads-as-written.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-11-peter.maydell@linaro.org
Commit: fee887a7b067faf1f9bc2d6c1d5fef787aadaf4a
https://github.com/qemu/qemu/commit/fee887a7b067faf1f9bc2d6c1d5fef787aadaf4a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI
On the MPS2 boards, the first 32 interrupt lines are entirely
internal to the SSE; interrupt lines for devices outside the SSE
start at 32. In the application notes that document each FPGA image,
the interrupt wiring is documented from the point of view of the CPU,
so '0' is the first of the SSE's interrupts and the devices in the
FPGA image itself are '32' and up: so the UART 0 Receive interrupt is
32, the SPI #0 interrupt is 51, and so on.
Within our implementation, because the external interrupts must be
connected to the EXP_IRQ[0...n] lines of the SSE object, we made the
get_sse_irq_in() function take an irqno whose values start at 0 for
the first FPGA device interrupt. In this numbering scheme the UART 0
Receive interrupt is 0, the SPI #0 interrupt is 19, and so on.
The result of these two different numbering schemes has been that
half of the devices were wired up to the wrong IRQs: the UART IRQs
are wired up correctly, but the DMA and SPI devices were passing
start-at-32 values to get_sse_irq_in() and so being mis-connected.
Fix the bug by making get_sse_irq_in() take values specified with the
same scheme that the hardware manuals use, to avoid confusion.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-12-peter.maydell@linaro.org
Commit: 424182791bae6dc9526b7e6d149848f237dbc046
https://github.com/qemu/qemu/commit/424182791bae6dc9526b7e6d149848f237dbc046
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts
The mps2-tz code uses PPCPortInfo data structures to define what
devices are present and how they are wired up. Currently we use
these to specify device types and addresses, but hard-code the
interrupt line wiring in each make_* helper function. This works for
the two boards we have at the moment, but the AN524 has some devices
with different interrupt assignments.
This commit adds the framework to allow PPCPortInfo structures to
specify interrupt numbers. We add an array of interrupt numbers to
the PPCPortInfo struct, and pass it through to the make_* helpers.
The following commit will change the make_* helpers over to using the
framework.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-13-peter.maydell@linaro.org
Commit: b22c4e8b960d96e4bbed35d64e017c21f5b5fb41
https://github.com/qemu/qemu/commit/b22c4e8b960d96e4bbed35d64e017c21f5b5fb41
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Move device IRQ info to data structures
Move the specification of the IRQ information for the uart, ethernet,
dma and spi devices to the data structures. (The other devices
handled by the PPCPortInfo structures don't have any interrupt lines
we need to wire up.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-14-peter.maydell@linaro.org
Commit: 8cf68ed9354f3ca68b237ed4fff13c108f0d56dd
https://github.com/qemu/qemu/commit/8cf68ed9354f3ca68b237ed4fff13c108f0d56dd
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs
We create an OR gate to wire together the overflow IRQs for all the
UARTs on the board; this has to have twice the number of inputs as
there are UARTs, since each UART feeds it a TX overflow and an RX
overflow interrupt line. Replace the hardcoded '10' with a
calculation based on the size of the uart[] array in the
MPS2TZMachineState. (We rely on OR gate inputs that are never wired
up or asserted being treated as always-zero.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-15-peter.maydell@linaro.org
Commit: ef29e3826be152996b8388656bc9d0dcfc2d43df
https://github.com/qemu/qemu/commit/ef29e3826be152996b8388656bc9d0dcfc2d43df
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Allow boards to have different PPCInfo data
The AN505 and AN521 have the same device layout, but the AN524 is
somewhat different. Allow for more than one PPCInfo array, which can
be selected based on the board type.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-16-peter.maydell@linaro.org
Commit: 4fec32db9c23ac7d04a0d0936b1d3b1b3413f280
https://github.com/qemu/qemu/commit/4fec32db9c23ac7d04a0d0936b1d3b1b3413f280
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Make RAM arrangement board-specific
The AN505 and AN521 have the same layout of RAM; the AN524 does not.
Replace the current hard-coding of where the RAM is and which parts
of it are behind which MPCs with a data-driven approach.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-17-peter.maydell@linaro.org
Commit: 18a8c3b390550601e5b88cf78e416353d23bc1eb
https://github.com/qemu/qemu/commit/18a8c3b390550601e5b88cf78e416353d23bc1eb
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data
Instead of hardcoding the MachineClass default_ram_size and
default_ram_id fields, set them on class creation by finding the
entry in the RAMInfo array which is marked as being the QEMU system
RAM.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-18-peter.maydell@linaro.org
Commit: b89918fceb4041466d8a98400f173fb583f74899
https://github.com/qemu/qemu/commit/b89918fceb4041466d8a98400f173fb583f74899
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Support ROMs as well as RAMs
The AN505 and AN521 don't have any read-only memory, but the AN524
does; add a flag to ROMInfo to mark a region as ROM.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-19-peter.maydell@linaro.org
Commit: a113aef998fe02154d2c95f34d38975648011dbb
https://github.com/qemu/qemu/commit/a113aef998fe02154d2c95f34d38975648011dbb
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo
The armv7m_load_kernel() function takes a mem_size argument which it
expects to be the size of the memory region at guest address 0. (It
uses this argument only as a limit on how large a raw image file it
can load at address zero).
Instead of hardcoding this value, find the RAMInfo corresponding to
the 0 address and extract its size.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-20-peter.maydell@linaro.org
Commit: 9c586cd54e7873e3139dae095f40715205a0d2c0
https://github.com/qemu/qemu/commit/9c586cd54e7873e3139dae095f40715205a0d2c0
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Add new mps3-an524 board
Add support for the mps3-an524 board; this is an SSE-200 based FPGA
image, like the existing mps2-an521. It has a usefully larger amount
of RAM, and a PL031 RTC, as well as some more minor differences.
In real hardware this image runs on a newer generation of the FPGA
board, the MPS3 rather than the older MPS2. Architecturally the two
boards are similar, so we implement the MPS3 boards in the mps2-tz.c
file as variations of the existing MPS2 boards.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-21-peter.maydell@linaro.org
Commit: 454f2b4495d521fa81cbab8dc6f83f2d309693f0
https://github.com/qemu/qemu/commit/454f2b4495d521fa81cbab8dc6f83f2d309693f0
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Stub out USB controller for mps3-an524
The AN524 has a USB controller (an ISP1763); we don't have a model of
it but we should provide a stub "unimplemented-device" for it. This
is slightly complicated because the USB controller shares a PPC port
with the ethernet controller.
Implement a make_* function which provides creates a container
MemoryRegion with both the ethernet controller and an
unimplemented-device stub for the USB controller.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-22-peter.maydell@linaro.org
Commit: d211c28dc7a5e31791697c7da578665b9cc15441
https://github.com/qemu/qemu/commit/d211c28dc7a5e31791697c7da578665b9cc15441
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524
The AN524 has a PL031 RTC, which we have a model of; provide it
rather than an unimplemented-device stub.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-23-peter.maydell@linaro.org
Commit: 94c78467bb445044013e9fed80e9d9e9175fb1ff
https://github.com/qemu/qemu/commit/94c78467bb445044013e9fed80e9d9e9175fb1ff
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M docs/system/arm/mps2.rst
Log Message:
-----------
docs/system/arm/mps2.rst: Document the new mps3-an524 board
Add brief documentation of the new mps3-an524 board.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-24-peter.maydell@linaro.org
Commit: d2d837d68f7c493e4bc306a237d7f72db88a0201
https://github.com/qemu/qemu/commit/d2d837d68f7c493e4bc306a237d7f72db88a0201
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
M hw/misc/armsse-cpuid.c
M hw/misc/armsse-mhu.c
M hw/misc/iotkit-sysctl.c
M hw/misc/iotkit-sysinfo.c
M hw/misc/mps2-fpgaio.c
M hw/misc/mps2-scc.c
M include/hw/arm/armsse.h
M include/hw/misc/armsse-cpuid.h
M include/hw/misc/armsse-mhu.h
M include/hw/misc/iotkit-secctl.h
M include/hw/misc/iotkit-sysctl.h
M include/hw/misc/iotkit-sysinfo.h
M include/hw/misc/mps2-fpgaio.h
Log Message:
-----------
hw/arm/mps2: Update old infocenter.arm.com URLs
Update old infocenter.arm.com URLs to the equivalent developer.arm.com
ones (the old URLs should redirect, but we might as well avoid the
redirection notice, and the new URLs are pleasantly shorter).
This commit covers the links to the MPS2 board TRM, the various
Application Notes, the IoTKit and SSE-200 documents.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-25-peter.maydell@linaro.org
Commit: 0273df0390046f9eba16b7e4e25f186664a5cd94
https://github.com/qemu/qemu/commit/0273df0390046f9eba16b7e4e25f186664a5cd94
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M docs/system/arm/mps2.rst
M docs/system/arm/nuvoton.rst
M hw/arm/mps2-tz.c
M hw/arm/mps2.c
M hw/arm/musicpal.c
M hw/arm/npcm7xx.c
M hw/arm/sbsa-ref.c
M hw/arm/xlnx-zynqmp.c
R hw/display/omap_lcd_template.h
M hw/display/omap_lcdc.c
M hw/display/tc6393xb.c
R hw/display/tc6393xb_template.h
M hw/display/tcx.c
M hw/i2c/npcm7xx_smbus.c
M hw/misc/armsse-cpuid.c
M hw/misc/armsse-mhu.c
M hw/misc/iotkit-sysctl.c
M hw/misc/iotkit-sysinfo.c
M hw/misc/mps2-fpgaio.c
M hw/misc/mps2-scc.c
M hw/net/meson.build
A hw/net/npcm7xx_emc.c
M hw/net/trace-events
M hw/virtio/virtio-mmio.c
M include/hw/arm/armsse.h
M include/hw/arm/npcm7xx.h
M include/hw/arm/xlnx-zynqmp.h
M include/hw/misc/armsse-cpuid.h
M include/hw/misc/armsse-mhu.h
M include/hw/misc/iotkit-secctl.h
M include/hw/misc/iotkit-sysctl.h
M include/hw/misc/iotkit-sysinfo.h
M include/hw/misc/mps2-fpgaio.h
M include/hw/misc/mps2-scc.h
A include/hw/net/npcm7xx_emc.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/helper-a64.c
M target/arm/helper-a64.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/mte_helper.c
M target/arm/translate-a64.c
M target/arm/vec_helper.c
M tests/qtest/meson.build
A tests/qtest/npcm7xx_emc-test.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210306'
into staging
* sbsa-ref: remove cortex-a53 from list of supported cpus
* sbsa-ref: add 'max' to list of allowed cpus
* target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe
* npcm7xx: add EMC model
* xlnx-zynqmp: Remove obsolete 'has_rpu' property
* target/arm: Speed up aarch64 TBL/TBX
* virtio-mmio: improve virtio-mmio get_dev_path alog
* target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks
* target/arm: Restrict v8M IDAU to TCG
* target/arm/cpu: Update coding style to make checkpatch.pl happy
* musicpal, tc6393xb, omap_lcdc, tcx: drop dead code for non-32-bit-RGB
surfaces
* Add new board: mps3-an524
# gpg: Signature made Sat 06 Mar 2021 13:49:46 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210306: (49 commits)
hw/arm/mps2: Update old infocenter.arm.com URLs
docs/system/arm/mps2.rst: Document the new mps3-an524 board
hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524
hw/arm/mps2-tz: Stub out USB controller for mps3-an524
hw/arm/mps2-tz: Add new mps3-an524 board
hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo
hw/arm/mps2-tz: Support ROMs as well as RAMs
hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data
hw/arm/mps2-tz: Make RAM arrangement board-specific
hw/arm/mps2-tz: Allow boards to have different PPCInfo data
hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs
hw/arm/mps2-tz: Move device IRQ info to data structures
hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts
hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI
hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524
hw/arm/mps2-tz: Make number of IRQs board-specific
hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type
hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board
hw/misc/mps2-fpgaio: Support SWITCH register
hw/misc/mps2-fpgaio: Make number of LEDs configurable by board
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/11b95b4d7fb3...0273df039004
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