[Qemu-commits] [qemu/qemu] 4f335a: sbsa-ref: remove cortex-a53 from list

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[Qemu-commits] [qemu/qemu] 4f335a: sbsa-ref: remove cortex-a53 from list

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 4f335a: sbsa-ref: remove cortex-a53 from list of supported...
Date:	Sat, 06 Mar 2021 03:23:35 -0800
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 4f335a6381f83beb5d6ac0d3993514379454a99d
      
https://github.com/qemu/qemu/commit/4f335a6381f83beb5d6ac0d3993514379454a99d
  Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/sbsa-ref.c

  Log Message:
  -----------
  sbsa-ref: remove cortex-a53 from list of supported cpus

Cortex-A53 supports 40bits of address space. sbsa-ref's memory starts
above this limit.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Leif Lindholm <leif@nuviainc.com>
Message-id: 20210216150122.3830863-2-marcin.juszkiewicz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: cecc0962099b4967473383bf28f12bef47e62cca
      
https://github.com/qemu/qemu/commit/cecc0962099b4967473383bf28f12bef47e62cca
  Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/sbsa-ref.c

  Log Message:
  -----------
  sbsa-ref: add 'max' to list of allowed cpus

Let add 'max' cpu while work goes on adding newer CPU types than
Cortex-A72. This allows us to check SVE etc support.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Acked-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210216150122.3830863-3-marcin.juszkiewicz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f2f68a78b793808b84367bc708d632969d4440aa
      
https://github.com/qemu/qemu/commit/f2f68a78b793808b84367bc708d632969d4440aa
  Author: Rebecca Cran <rebecca@nuviainc.com>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe

Add support for FEAT_SSBS. SSBS (Speculative Store Bypass Safe) is an
optional feature in ARMv8.0, and mandatory in ARMv8.5.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210216224543.16142-2-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 89455d1ba6ed190e840cb732e63958755ea42a07
      
https://github.com/qemu/qemu/commit/89455d1ba6ed190e840cb732e63958755ea42a07
  Author: Rebecca Cran <rebecca@nuviainc.com>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU

Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210216224543.16142-3-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ed84a60ca80c403749c1fc1bab27c85d8edba39d
      
https://github.com/qemu/qemu/commit/ed84a60ca80c403749c1fc1bab27c85d8edba39d
  Author: Rebecca Cran <rebecca@nuviainc.com>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU

Enable FEAT_SSBS for the "max" 32-bit CPU.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210216224543.16142-4-rebecca@nuviainc.com
[PMM: fix typo causing compilation failure]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 01c966b54f5effd7132da1a8d33ae1927944cfdf
      
https://github.com/qemu/qemu/commit/01c966b54f5effd7132da1a8d33ae1927944cfdf
  Author: Doug Evans <dje@google.com>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/net/meson.build
    A hw/net/npcm7xx_emc.c
    M hw/net/trace-events
    A include/hw/net/npcm7xx_emc.h

  Log Message:
  -----------
  hw/net: Add npcm7xx emc model

This is a 10/100 ethernet device that has several features.
Only the ones needed by the Linux driver have been implemented.
See npcm7xx_emc.c for a list of unimplemented features.

Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com>
Signed-off-by: Doug Evans <dje@google.com>
Message-id: 20210218212453.831406-2-dje@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7758643650f0229bd3ccd23112c255664445eabd
      
https://github.com/qemu/qemu/commit/7758643650f0229bd3ccd23112c255664445eabd
  Author: Doug Evans <dje@google.com>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M docs/system/arm/nuvoton.rst
    M hw/arm/npcm7xx.c
    M include/hw/arm/npcm7xx.h

  Log Message:
  -----------
  hw/arm: Add npcm7xx emc model

This is a 10/100 ethernet device that has several features.
Only the ones needed by the Linux driver have been implemented.
See npcm7xx_emc.c for a list of unimplemented features.

Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Doug Evans <dje@google.com>
Message-id: 20210218212453.831406-3-dje@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e6646167cc390388a330fe94b9af4d5e8e0cb2d9
      
https://github.com/qemu/qemu/commit/e6646167cc390388a330fe94b9af4d5e8e0cb2d9
  Author: Doug Evans <dje@google.com>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M tests/qtest/meson.build
    A tests/qtest/npcm7xx_emc-test.c

  Log Message:
  -----------
  tests/qtests: Add npcm7xx emc model test

Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Doug Evans <dje@google.com>
Message-id: 20210218212453.831406-4-dje@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4565afbbf0b6d897ee746f2410d60460f43c3159
      
https://github.com/qemu/qemu/commit/4565afbbf0b6d897ee746f2410d60460f43c3159
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  hw/arm/xlnx-zynqmp: Remove obsolete 'has_rpu' property

We hint the 'has_rpu' property is no longer required since commit
6908ec448b4 ("xlnx-zynqmp: Properly support the smp command line
option") which was released in QEMU v2.11.0.

Beside, this device is marked 'user_creatable = false', so the
only thing that could be setting the property is the board code
that creates the device.

Since the property is not user-facing, we can remove it without
going through the deprecation process.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210219144350.1979905-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 519183d3fee58e52f7b51cf146c9dc9edc565059
      
https://github.com/qemu/qemu/commit/519183d3fee58e52f7b51cf146c9dc9edc565059
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/translate-a64.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Speed up aarch64 TBL/TBX

Always perform one call instead of two for 16-byte operands.
Use byte loads/stores directly into the vector register file
instead of extractions and deposits to a 64-bit local variable.

In order to easily receive pointers into the vector register file,
convert the helper to the gvec out-of-line signature.  Move the
helper into vec_helper.c, where it can make use of H1 and clear_tail.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20210224230532.276878-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5dfbfefaada495b9a65382d64f06325fd802c717
      
https://github.com/qemu/qemu/commit/5dfbfefaada495b9a65382d64f06325fd802c717
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/i2c/npcm7xx_smbus.c

  Log Message:
  -----------
  hw/i2c/npcm7xx_smbus: Simplify npcm7xx_smbus_init()

The STATUS register will be reset to IDLE in
cnpcm7xx_smbus_enter_reset(), no need to preset
it in instance_init().

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20210228224813.312532-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 819b3496196c2a7de89ed2372182c24053443990
      
https://github.com/qemu/qemu/commit/819b3496196c2a7de89ed2372182c24053443990
  Author: schspa <schspa@gmail.com>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/virtio/virtio-mmio.c

  Log Message:
  -----------
  virtio-mmio: improve virtio-mmio get_dev_path alog

At the moment the following QEMU command line triggers an assertion
failure On xlnx-versal SOC:
  qemu-system-aarch64 \
      -machine xlnx-versal-virt -nographic -smp 2 -m 128 \
      -fsdev local,id=shareid,path=${HOME}/work,security_model=none \
      -device virtio-9p-device,fsdev=shareid,mount_tag=share \
      -fsdev local,id=shareid1,path=${HOME}/Music,security_model=none \
      -device virtio-9p-device,fsdev=shareid1,mount_tag=share1

  qemu-system-aarch64: ../migration/savevm.c:860:
  vmstate_register_with_alias_id:
  Assertion `!se->compat || se->instance_id == 0' failed.

This problem was fixed on arm virt platform in commit f58b39d2d5b
("virtio-mmio: format transport base address in BusClass.get_dev_path")

It works perfectly on arm virt platform. but there is still there on
xlnx-versal SOC.

The main difference between arm virt and xlnx-versal is they use
different way to create virtio-mmio qdev. on arm virt, it calls
sysbus_create_simple("virtio-mmio", base, pic[irq]); which will call
sysbus_mmio_map internally and assign base address to subsys device
mmio correctly. but xlnx-versal's implements won't do this.

However, xlnx-versal can't switch to sysbus_create_simple() to create
virtio-mmio device. It's because xlnx-versal's cpu use
VersalVirt.soc.fpd.apu.mr as it's memory. which is subregion of
system_memory. sysbus_create_simple will add virtio to system_memory,
which can't be accessed by cpu.

Besides, xlnx-versal can't add sysbus_mmio_map api call too, because
this will add memory region to system_memory, and it can't be added
to VersalVirt.soc.fpd.apu.mr again.

We can solve this by assign correct base address offset on dev_path.

This path was test on aarch64 virt & xlnx-versal platform.

Signed-off-by: schspa <schspa@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2d928adf8a9148510e1b2041145b8a873f4d26df
      
https://github.com/qemu/qemu/commit/2d928adf8a9148510e1b2041145b8a873f4d26df
  Author: Peter Collingbourne <pcc@google.com>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M target/arm/helper.c
    M target/arm/mte_helper.c

  Log Message:
  -----------
  target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks

Section D6.7 of the ARM ARM states:

For the purpose of determining Tag Check Fault handling, unprivileged
load and store instructions are treated as if executed at EL0 when
executed at either:
- EL1, when the Effective value of PSTATE.UAO is 0.
- EL2, when both the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}
  and the Effective value of PSTATE.UAO is 0.

ARM has confirmed a defect in the pseudocode function
AArch64.TagCheckFault that makes it inconsistent with the above
wording. The remedy is to adjust references to PSTATE.EL in that
function to instead refer to AArch64.AccessUsesEL(acctype), so
that unprivileged instructions use SCTLR_EL1.TCF0 and TFSRE0_EL1.
The exception type for synchronous tag check faults remains unchanged.

This patch implements the described change by partially reverting
commits 50244cc76abc and cc97b0019bb5.

Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219201820.2672077-1-pcc@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6e937ba7f8fb90d66cb3781f7fed32fb4239556a
      
https://github.com/qemu/qemu/commit/6e937ba7f8fb90d66cb3781f7fed32fb4239556a
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu_tcg.c

  Log Message:
  -----------
  target/arm: Restrict v8M IDAU to TCG

IDAU is specific to M-profile. KVM only supports A-profile.
Restrict this interface to TCG, as it is pointless (and
confusing) on a KVM-only build.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210221222617.2579610-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: dddc200dcddd1a4e44c32e2b0f5a3cb248c506a6
      
https://github.com/qemu/qemu/commit/dddc200dcddd1a4e44c32e2b0f5a3cb248c506a6
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm/cpu: Update coding style to make checkpatch.pl happy

We will move this code in the next commit. Clean it up
first to avoid checkpatch.pl errors.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210221222617.2579610-3-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9aee50eefba8c39d17759c7def3ba5a899c86271
      
https://github.com/qemu/qemu/commit/9aee50eefba8c39d17759c7def3ba5a899c86271
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/musicpal.c

  Log Message:
  -----------
  hw/arm/musicpal: Remove dead code for non-32-bit-RGB surfaces

For a long time now the UI layer has guaranteed that the console
surface is always 32 bits per pixel RGB. Remove the legacy dead
code from the milkymist display device which was handling the
possibility that the console surface was some other format.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215103215.4944-2-peter.maydell@linaro.org


  Commit: 21c231d7c8872b0ba800c6e8734c15b4ccaf34fb
      
https://github.com/qemu/qemu/commit/21c231d7c8872b0ba800c6e8734c15b4ccaf34fb
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/display/tc6393xb.c
    M include/ui/console.h

  Log Message:
  -----------
  hw/display/tc6393xb: Remove dead code for handling non-32bpp surfaces

For a long time now the UI layer has guaranteed that the console
surface is always 32 bits per pixel RGB. Remove the legacy dead
code from the tc6393xb display device which was handling the
possibility that the console surface was some other format.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215103215.4944-3-peter.maydell@linaro.org


  Commit: 38da138b5903d0e90ab066a16847b0cff9777e93
      
https://github.com/qemu/qemu/commit/38da138b5903d0e90ab066a16847b0cff9777e93
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/display/tc6393xb_template.h

  Log Message:
  -----------
  hw/display/tc6393xb: Expand out macros in template header

Now the template header is included only for BITS==32, expand
out all the macros that depended on the BITS setting.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215103215.4944-4-peter.maydell@linaro.org


  Commit: cd067fa7c3e0d09c26ae2e0bf4210e151b2b5395
      
https://github.com/qemu/qemu/commit/cd067fa7c3e0d09c26ae2e0bf4210e151b2b5395
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/display/tc6393xb.c
    R hw/display/tc6393xb_template.h

  Log Message:
  -----------
  hw/display/tc6393xb: Inline tc6393xb_draw_graphic32() at its callsite

The function tc6393xb_draw_graphic32() is called in exactly one place,
so just inline the function body at its callsite. This allows us to
drop the template header entirely.

The code move includes a single added space after 'for' to fix
the coding style.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210215103215.4944-5-peter.maydell@linaro.org


  Commit: 83b319bfdc3c0776e8df4f855906dc3203a9aab3
      
https://github.com/qemu/qemu/commit/83b319bfdc3c0776e8df4f855906dc3203a9aab3
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/display/omap_lcd_template.h

  Log Message:
  -----------
  hw/display/omap_lcdc: Expand out macros in template header

The omap_lcdc template header is already only included once, for
DEPTH==32, but it still has all the macro-driven parameterization
for other depths. Expand out all the macros in the header.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210215103215.4944-6-peter.maydell@linaro.org


  Commit: 36bc11b5b6daff3517a49d020940159301d87ae1
      
https://github.com/qemu/qemu/commit/36bc11b5b6daff3517a49d020940159301d87ae1
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/display/omap_lcd_template.h

  Log Message:
  -----------
  hw/display/omap_lcdc: Drop broken bigendian ifdef

The draw_line16_32() function in the omap_lcdc template header
includes an ifdef for the case where HOST_WORDS_BIGENDIAN matches
TARGET_WORDS_BIGENDIAN.  This is trying to optimise for "source
bitmap and destination bitmap format match", but it is broken,
because in this function the formats don't match: the source is
16-bit colour and the destination is 32-bit colour, so a memcpy()
will produce corrupted graphics output.  Drop the bogus ifdef.

This bug was introduced in commit ea644cf343129, when we dropped
support for DEPTH values other than 32 from the template header.
The old #if line was
  #if DEPTH == 16 && defined(HOST_WORDS_BIGENDIAN) == 
defined(TARGET_WORDS_BIGENDIAN)
and this was mistakenly changed to
  #if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
rather than deleting the #if as now having an always-false condition.

Fixes: ea644cf343129
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210215103215.4944-7-peter.maydell@linaro.org


  Commit: f359c4d0a223f099ffe1f0fb99016b173b5b8601
      
https://github.com/qemu/qemu/commit/f359c4d0a223f099ffe1f0fb99016b173b5b8601
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/display/omap_lcd_template.h

  Log Message:
  -----------
  hw/display/omap_lcdc: Fix coding style issues in template header

Fix some minor coding style issues in the template header,
so checkpatch doesn't complain when we move the code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210215103215.4944-8-peter.maydell@linaro.org


  Commit: 4b32d2f50d5c956efa9e43e2d33097ed44f634a3
      
https://github.com/qemu/qemu/commit/4b32d2f50d5c956efa9e43e2d33097ed44f634a3
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    R hw/display/omap_lcd_template.h
    M hw/display/omap_lcdc.c

  Log Message:
  -----------
  hw/display/omap_lcdc: Inline template header into C file

We only include the template header once, so just inline it into the
source file for the device.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210215103215.4944-9-peter.maydell@linaro.org


  Commit: 6b1d08aab681004616986c9fa6392114a0eff1d4
      
https://github.com/qemu/qemu/commit/6b1d08aab681004616986c9fa6392114a0eff1d4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/display/omap_lcdc.c

  Log Message:
  -----------
  hw/display/omap_lcdc: Delete unnecessary macro

The macro draw_line_func is used only once; just expand it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210215103215.4944-10-peter.maydell@linaro.org


  Commit: abfe6db82e5b11148cf4e486a3c393828f387e5f
      
https://github.com/qemu/qemu/commit/abfe6db82e5b11148cf4e486a3c393828f387e5f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/display/tcx.c

  Log Message:
  -----------
  hw/display/tcx: Drop unnecessary code for handling BGR format outputs

For a long time now the UI layer has guaranteed that the console
surface is always 32 bits per pixel, RGB. The TCX code already
assumes 32bpp, but it still has some checks of is_surface_bgr()
in an attempt to support 32bpp BGR. is_surface_bgr() will always
return false for the qemu_console_surface(), unless the display
device itself has deliberately created an alternate-format
surface via a function like qemu_create_displaysurface_from().

Drop the never-used BGR-handling code, and assert that we have
a 32-bit surface rather than just doing nothing if it isn't.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215102149.20513-1-peter.maydell@linaro.org


  Commit: 132e42fdd4a22c90289358542ca08581b938b6f2
      
https://github.com/qemu/qemu/commit/132e42fdd4a22c90289358542ca08581b938b6f2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Make SYSCLK frequency board-specific

The AN524 has a different SYSCLK frequency from the AN505 and AN521;
make the SYSCLK frequency a field in the MPS2TZMachineClass rather
than a compile-time constant so we can support the AN524.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-2-peter.maydell@linaro.org


  Commit: b709ca37333112196c032379658cb86d4479fb60
      
https://github.com/qemu/qemu/commit/b709ca37333112196c032379658cb86d4479fb60
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c
    M hw/arm/mps2.c
    M hw/misc/mps2-scc.c
    M include/hw/misc/mps2-scc.h

  Log Message:
  -----------
  hw/misc/mps2-scc: Support configurable number of OSCCLK values

Currently the MPS2 SCC device implements a fixed number of OSCCLK
values (3).  The variant of this device in the MPS3 AN524 board has 6
OSCCLK values.  Switch to using a PROP_ARRAY, which allows board code
to specify how large the OSCCLK array should be as well as its
values.

With a variable-length property array, the SCC no longer specifies
default values for the OSCCLKs, so we must set them explicitly in the
board code.  This defaults are actually incorrect for the an521 and
an505; we will correct this bug in a following patch.

This is a migration compatibility break for all the mps boards.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-3-peter.maydell@linaro.org


  Commit: 9afbdc9126e34df8880645a28e0b969a9608af79
      
https://github.com/qemu/qemu/commit/9afbdc9126e34df8880645a28e0b969a9608af79
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511

We were previously using the default OSCCLK settings, which are
correct for the older MPS2 boards (mps2-an385, mps2-an386,
mps2-an500, mps2-an511), but wrong for the mps2-an505 and mps2-511
implemented in mps2-tz.c.  Now we're setting the values explicitly we
can fix them to be correct.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-4-peter.maydell@linaro.org


  Commit: c440c328ba267485172cfa582561738de1daa76a
      
https://github.com/qemu/qemu/commit/c440c328ba267485172cfa582561738de1daa76a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board

The AN505 and AN511 happen to share the same OSCCLK values, but the
AN524 will have a different set (and more of them), so split the
settings out to be per-board.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-5-peter.maydell@linaro.org


  Commit: fd6013663e4547795efc9ffc4aeae1d6db384e88
      
https://github.com/qemu/qemu/commit/fd6013663e4547795efc9ffc4aeae1d6db384e88
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/misc/mps2-fpgaio.c
    M include/hw/misc/mps2-fpgaio.h

  Log Message:
  -----------
  hw/misc/mps2-fpgaio: Make number of LEDs configurable by board

The MPS2 board has 2 LEDs, but the MPS3 board has 10 LEDs.  The
FPGAIO device is similar on both sets of boards, but the LED0
register has correspondingly more bits that have an effect.  Add a
device property for number of LEDs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-6-peter.maydell@linaro.org


  Commit: 2c64b0a57f61da4251d921186483c66ea403941a
      
https://github.com/qemu/qemu/commit/2c64b0a57f61da4251d921186483c66ea403941a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/misc/mps2-fpgaio.c
    M include/hw/misc/mps2-fpgaio.h

  Log Message:
  -----------
  hw/misc/mps2-fpgaio: Support SWITCH register

MPS3 boards have an extra SWITCH register in the FPGAIO block which
reports the value of some switches.  Implement this, governed by a
property the board code can use to specify whether whether it exists.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-7-peter.maydell@linaro.org


  Commit: 8730535edb561c85f51d2c8edb24913d795b8698
      
https://github.com/qemu/qemu/commit/8730535edb561c85f51d2c8edb24913d795b8698
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board

Set the FPGAIO num-leds and have-switches properties explicitly
per-board, rather than relying on the defaults.  The AN505 and AN521
both have the same settings as the default values, but the AN524 will
be different.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-8-peter.maydell@linaro.org


  Commit: d07afe7599c8a936da34a2ffba9630611d4bf697
      
https://github.com/qemu/qemu/commit/d07afe7599c8a936da34a2ffba9630611d4bf697
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type

In the mps2-tz board code, we handle devices whose interrupt lines
must be wired to all CPUs by creating IRQ splitter devices for the
AN521, because it has 2 CPUs, but wiring the device IRQ directly to
the SSE/IoTKit input for the AN505, which has only 1 CPU.

We can avoid making an explicit check on the board type constant by
instead creating and using the IRQ splitters for any board with more
than 1 CPU.  This avoids having to add extra cases to the
conditionals every time we add new boards.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-9-peter.maydell@linaro.org


  Commit: 6bdbf3a839b8150328776b06a90abc0508e6c25f
      
https://github.com/qemu/qemu/commit/6bdbf3a839b8150328776b06a90abc0508e6c25f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Make number of IRQs board-specific

The AN524 has more interrupt lines than the AN505 and AN521; make
numirq board-specific rather than a compile-time constant.

Since the difference is small (92 on the current boards and 95 on the
new one) we don't dynamically allocate the cpu_irq_splitter[] array
but leave it as a fixed length array whose size is the maximum needed
for any of the boards.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-10-peter.maydell@linaro.org


  Commit: ff355033ca2541e322b23387801a10eb4475a964
      
https://github.com/qemu/qemu/commit/ff355033ca2541e322b23387801a10eb4475a964
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/misc/mps2-scc.c
    M include/hw/misc/mps2-scc.h

  Log Message:
  -----------
  hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524

The AN524 version of the SCC interface has different behaviour for
some of the CFG registers; implement it.

Each board in this family can have minor differences in the meaning
of the CFG registers, so rather than trying to specify all the
possible semantics via individual device properties, we make the
behaviour conditional on the part-number field of the SCC_ID register
which the board code already passes us.

For the AN524, the differences are:
 * CFG3 is reserved rather than being board switches
 * CFG5 is a new register ("ACLK Frequency in Hz")
 * CFG6 is a new register ("Clock divider for BRAM")

We implement both of the new registers as reads-as-written.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-11-peter.maydell@linaro.org


  Commit: 4a8b3f654b185da13a6796b2913ef79f6efe3661
      
https://github.com/qemu/qemu/commit/4a8b3f654b185da13a6796b2913ef79f6efe3661
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI

On the MPS2 boards, the first 32 interrupt lines are entirely
internal to the SSE; interrupt lines for devices outside the SSE
start at 32.  In the application notes that document each FPGA image,
the interrupt wiring is documented from the point of view of the CPU,
so '0' is the first of the SSE's interrupts and the devices in the
FPGA image itself are '32' and up: so the UART 0 Receive interrupt is
32, the SPI #0 interrupt is 51, and so on.

Within our implementation, because the external interrupts must be
connected to the EXP_IRQ[0...n] lines of the SSE object, we made the
get_sse_irq_in() function take an irqno whose values start at 0 for
the first FPGA device interrupt.  In this numbering scheme the UART 0
Receive interrupt is 0, the SPI #0 interrupt is 19, and so on.

The result of these two different numbering schemes has been that
half of the devices were wired up to the wrong IRQs: the UART IRQs
are wired up correctly, but the DMA and SPI devices were passing
start-at-32 values to get_sse_irq_in() and so being mis-connected.

Fix the bug by making get_sse_irq_in() take values specified with the
same scheme that the hardware manuals use, to avoid confusion.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-12-peter.maydell@linaro.org


  Commit: 61db91da0117388e3895f4813dd3e923c7f8b09f
      
https://github.com/qemu/qemu/commit/61db91da0117388e3895f4813dd3e923c7f8b09f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts

The mps2-tz code uses PPCPortInfo data structures to define what
devices are present and how they are wired up.  Currently we use
these to specify device types and addresses, but hard-code the
interrupt line wiring in each make_* helper function.  This works for
the two boards we have at the moment, but the AN524 has some devices
with different interrupt assignments.

This commit adds the framework to allow PPCPortInfo structures to
specify interrupt numbers.  We add an array of interrupt numbers to
the PPCPortInfo struct, and pass it through to the make_* helpers.
The following commit will change the make_* helpers over to using the
framework.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-13-peter.maydell@linaro.org


  Commit: 8f2476de350f28a10a6bf672063934375bb74224
      
https://github.com/qemu/qemu/commit/8f2476de350f28a10a6bf672063934375bb74224
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Move device IRQ info to data structures

Move the specification of the IRQ information for the uart, ethernet,
dma and spi devices to the data structures.  (The other devices
handled by the PPCPortInfo structures don't have any interrupt lines
we need to wire up.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-14-peter.maydell@linaro.org


  Commit: b67f1b67c44e6bb75d5843a4360365b1262f4a6a
      
https://github.com/qemu/qemu/commit/b67f1b67c44e6bb75d5843a4360365b1262f4a6a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs

We create an OR gate to wire together the overflow IRQs for all the
UARTs on the board; this has to have twice the number of inputs as
there are UARTs, since each UART feeds it a TX overflow and an RX
overflow interrupt line.  Replace the hardcoded '10' with a
calculation based on the size of the uart[] array in the
MPS2TZMachineState.  (We rely on OR gate inputs that are never wired
up or asserted being treated as always-zero.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-15-peter.maydell@linaro.org


  Commit: eb5180505bfb1e74b5b5e3ea90d0d61951392765
      
https://github.com/qemu/qemu/commit/eb5180505bfb1e74b5b5e3ea90d0d61951392765
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Allow boards to have different PPCInfo data

The AN505 and AN521 have the same device layout, but the AN524 is
somewhat different.  Allow for more than one PPCInfo array, which can
be selected based on the board type.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-16-peter.maydell@linaro.org


  Commit: c5fb41899522ec7e931ad7062ad850a7a6e54745
      
https://github.com/qemu/qemu/commit/c5fb41899522ec7e931ad7062ad850a7a6e54745
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Make RAM arrangement board-specific

The AN505 and AN521 have the same layout of RAM; the AN524 does not.
Replace the current hard-coding of where the RAM is and which parts
of it are behind which MPCs with a data-driven approach.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-17-peter.maydell@linaro.org


  Commit: 565124a986998cd15eb62963693ea794cc526778
      
https://github.com/qemu/qemu/commit/565124a986998cd15eb62963693ea794cc526778
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data

Instead of hardcoding the MachineClass default_ram_size and
default_ram_id fields, set them on class creation by finding the
entry in the RAMInfo array which is marked as being the QEMU system
RAM.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-18-peter.maydell@linaro.org


  Commit: e301a164da31408e74cfbc5fa0eb50147b6eaf50
      
https://github.com/qemu/qemu/commit/e301a164da31408e74cfbc5fa0eb50147b6eaf50
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Support ROMs as well as RAMs

The AN505 and AN521 don't have any read-only memory, but the AN524
does; add a flag to ROMInfo to mark a region as ROM.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-19-peter.maydell@linaro.org


  Commit: 53318e6ddc2e2085836f17eb877e797c8d46d11b
      
https://github.com/qemu/qemu/commit/53318e6ddc2e2085836f17eb877e797c8d46d11b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo

The armv7m_load_kernel() function takes a mem_size argument which it
expects to be the size of the memory region at guest address 0.  (It
uses this argument only as a limit on how large a raw image file it
can load at address zero).

Instead of hardcoding this value, find the RAMInfo corresponding to
the 0 address and extract its size.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-20-peter.maydell@linaro.org


  Commit: 653303186c95933b5b5fd0ec8f3fbf2278c3110a
      
https://github.com/qemu/qemu/commit/653303186c95933b5b5fd0ec8f3fbf2278c3110a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Add new mps3-an524 board

Add support for the mps3-an524 board; this is an SSE-200 based FPGA
image, like the existing mps2-an521.  It has a usefully larger amount
of RAM, and a PL031 RTC, as well as some more minor differences.

In real hardware this image runs on a newer generation of the FPGA
board, the MPS3 rather than the older MPS2.  Architecturally the two
boards are similar, so we implement the MPS3 boards in the mps2-tz.c
file as variations of the existing MPS2 boards.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-21-peter.maydell@linaro.org


  Commit: e5eb36233c050027819a32e010b76aa09a7a162d
      
https://github.com/qemu/qemu/commit/e5eb36233c050027819a32e010b76aa09a7a162d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Stub out USB controller for mps3-an524

The AN524 has a USB controller (an ISP1763); we don't have a model of
it but we should provide a stub "unimplemented-device" for it.  This
is slightly complicated because the USB controller shares a PPC port
with the ethernet controller.

Implement a make_* function which provides creates a container
MemoryRegion with both the ethernet controller and an
unimplemented-device stub for the USB controller.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-22-peter.maydell@linaro.org


  Commit: 15b0d76af584b236a1ad55c31061171f92564157
      
https://github.com/qemu/qemu/commit/15b0d76af584b236a1ad55c31061171f92564157
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524

The AN524 has a PL031 RTC, which we have a model of; provide it
rather than an unimplemented-device stub.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-23-peter.maydell@linaro.org


  Commit: 54f271698d3294b523d88373b35f3f83c31544d3
      
https://github.com/qemu/qemu/commit/54f271698d3294b523d88373b35f3f83c31544d3
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M docs/system/arm/mps2.rst

  Log Message:
  -----------
  docs/system/arm/mps2.rst: Document the new mps3-an524 board

Add brief documentation of the new mps3-an524 board.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-24-peter.maydell@linaro.org


  Commit: 2c669ff88ec6733420a000103a2b8b9e93df4945
      
https://github.com/qemu/qemu/commit/2c669ff88ec6733420a000103a2b8b9e93df4945
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M hw/arm/mps2-tz.c
    M hw/misc/armsse-cpuid.c
    M hw/misc/armsse-mhu.c
    M hw/misc/iotkit-sysctl.c
    M hw/misc/iotkit-sysinfo.c
    M hw/misc/mps2-fpgaio.c
    M hw/misc/mps2-scc.c
    M include/hw/arm/armsse.h
    M include/hw/misc/armsse-cpuid.h
    M include/hw/misc/armsse-mhu.h
    M include/hw/misc/iotkit-secctl.h
    M include/hw/misc/iotkit-sysctl.h
    M include/hw/misc/iotkit-sysinfo.h
    M include/hw/misc/mps2-fpgaio.h

  Log Message:
  -----------
  hw/arm/mps2: Update old infocenter.arm.com URLs

Update old infocenter.arm.com URLs to the equivalent developer.arm.com
ones (the old URLs should redirect, but we might as well avoid the
redirection notice, and the new URLs are pleasantly shorter).

This commit covers the links to the MPS2 board TRM, the various
Application Notes, the IoTKit and SSE-200 documents.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-25-peter.maydell@linaro.org


  Commit: 11b95b4d7fb358fabf3eba07efb2d6cb04dd38df
      
https://github.com/qemu/qemu/commit/11b95b4d7fb358fabf3eba07efb2d6cb04dd38df
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-06 (Sat, 06 Mar 2021)

  Changed paths:
    M docs/system/arm/mps2.rst
    M docs/system/arm/nuvoton.rst
    M hw/arm/mps2-tz.c
    M hw/arm/mps2.c
    M hw/arm/musicpal.c
    M hw/arm/npcm7xx.c
    M hw/arm/sbsa-ref.c
    M hw/arm/xlnx-zynqmp.c
    R hw/display/omap_lcd_template.h
    M hw/display/omap_lcdc.c
    M hw/display/tc6393xb.c
    R hw/display/tc6393xb_template.h
    M hw/display/tcx.c
    M hw/i2c/npcm7xx_smbus.c
    M hw/misc/armsse-cpuid.c
    M hw/misc/armsse-mhu.c
    M hw/misc/iotkit-sysctl.c
    M hw/misc/iotkit-sysinfo.c
    M hw/misc/mps2-fpgaio.c
    M hw/misc/mps2-scc.c
    M hw/net/meson.build
    A hw/net/npcm7xx_emc.c
    M hw/net/trace-events
    M hw/virtio/virtio-mmio.c
    M include/hw/arm/armsse.h
    M include/hw/arm/npcm7xx.h
    M include/hw/arm/xlnx-zynqmp.h
    M include/hw/misc/armsse-cpuid.h
    M include/hw/misc/armsse-mhu.h
    M include/hw/misc/iotkit-secctl.h
    M include/hw/misc/iotkit-sysctl.h
    M include/hw/misc/iotkit-sysinfo.h
    M include/hw/misc/mps2-fpgaio.h
    M include/hw/misc/mps2-scc.h
    A include/hw/net/npcm7xx_emc.h
    M include/ui/console.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/cpu_tcg.c
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/mte_helper.c
    M target/arm/translate-a64.c
    M target/arm/vec_helper.c
    M tests/qtest/meson.build
    A tests/qtest/npcm7xx_emc-test.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210305' 
into staging

 * sbsa-ref: remove cortex-a53 from list of supported cpus
 * sbsa-ref: add 'max' to list of allowed cpus
 * target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe
 * npcm7xx: add EMC model
 * xlnx-zynqmp: Remove obsolete 'has_rpu' property
 * target/arm: Speed up aarch64 TBL/TBX
 * virtio-mmio: improve virtio-mmio get_dev_path alog
 * target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks
 * target/arm: Restrict v8M IDAU to TCG
 * target/arm/cpu: Update coding style to make checkpatch.pl happy
 * musicpal, tc6393xb, omap_lcdc, tcx: drop dead code for non-32-bit-RGB 
surfaces
 * Add new board: mps3-an524

# gpg: Signature made Fri 05 Mar 2021 17:14:06 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210305: (49 commits)
  hw/arm/mps2: Update old infocenter.arm.com URLs
  docs/system/arm/mps2.rst: Document the new mps3-an524 board
  hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524
  hw/arm/mps2-tz: Stub out USB controller for mps3-an524
  hw/arm/mps2-tz: Add new mps3-an524 board
  hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo
  hw/arm/mps2-tz: Support ROMs as well as RAMs
  hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data
  hw/arm/mps2-tz: Make RAM arrangement board-specific
  hw/arm/mps2-tz: Allow boards to have different PPCInfo data
  hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs
  hw/arm/mps2-tz: Move device IRQ info to data structures
  hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts
  hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI
  hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524
  hw/arm/mps2-tz: Make number of IRQs board-specific
  hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type
  hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board
  hw/misc/mps2-fpgaio: Support SWITCH register
  hw/misc/mps2-fpgaio: Make number of LEDs configurable by board
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/33615cec7bde...11b95b4d7fb3
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