[Qemu-commits] [qemu/qemu] c36c65: target/arm: ARMv8.4-TTST extension

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[Qemu-commits] [qemu/qemu] c36c65: target/arm: ARMv8.4-TTST extension

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] c36c65: target/arm: ARMv8.4-TTST extension
Date:	Tue, 12 Jan 2021 09:27:58 -0800
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: c36c65ea3c35b309d524c05a1c05fdeabf83ddd5
      
https://github.com/qemu/qemu/commit/c36c65ea3c35b309d524c05a1c05fdeabf83ddd5
  Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: ARMv8.4-TTST extension

This adds for the Small Translation tables extension in AArch64 state.

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 078e9fe3cbd6894fb6e420d8b53f304a3d5c0464
      
https://github.com/qemu/qemu/commit/078e9fe3cbd6894fb6e420d8b53f304a3d5c0464
  Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: enable Small Translation tables in max CPU

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9a286bcdfd2b04afca9a668a6d6e0feb809d2d63
      
https://github.com/qemu/qemu/commit/9a286bcdfd2b04afca9a668a6d6e0feb809d2d63
  Author: Leif Lindholm <leif@nuviainc.com>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: fix typo in cpu.h ID_AA64PFR1 field name

SBSS -> SSBS

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-2-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f6450bcb6b2d3e4beae77141edce9e99cb8c277e
      
https://github.com/qemu/qemu/commit/f6450bcb6b2d3e4beae77141edce9e99cb8c277e
  Author: Leif Lindholm <leif@nuviainc.com>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: make ARMCPU.clidr 64-bit

The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
32, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
Extend the clidr field to be able to hold this context.

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-3-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a5fd319ae7f6d496ff5448ec1dedcae8e2f59e9f
      
https://github.com/qemu/qemu/commit/a5fd319ae7f6d496ff5448ec1dedcae8e2f59e9f
  Author: Leif Lindholm <leif@nuviainc.com>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: make ARMCPU.ctr 64-bit

When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the
TminLine field in bits [37:32].
Extend the ctr field to be able to hold this context.

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-4-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2a14526a6f56973348d622abc572db377f5a23ef
      
https://github.com/qemu/qemu/commit/2a14526a6f56973348d622abc572db377f5a23ef
  Author: Leif Lindholm <leif@nuviainc.com>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-5-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 00a92832f453275ca023962c00a60dde3a4f2fed
      
https://github.com/qemu/qemu/commit/00a92832f453275ca023962c00a60dde3a4f2fed
  Author: Leif Lindholm <leif@nuviainc.com>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: add aarch64 ID register fields to cpu.h

Add entries present in ARM DDI 0487F.c (August 2020).

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-6-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: bd78b6be24f3ceb71f1a7ec2c98c7a5e49cb4a86
      
https://github.com/qemu/qemu/commit/bd78b6be24f3ceb71f1a7ec2c98c7a5e49cb4a86
  Author: Leif Lindholm <leif@nuviainc.com>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: add aarch32 ID register fields to cpu.h

Add entries present in ARM DDI 0487F.c (August 2020).

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-7-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8d6fda8c1072fbed2d030c34a5233f17913a3ba9
      
https://github.com/qemu/qemu/commit/8d6fda8c1072fbed2d030c34a5233f17913a3ba9
  Author: Roman Bolshakov <r.bolshakov@yadro.com>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M ui/cocoa.m

  Log Message:
  -----------
  ui/cocoa: Update path to docs in build tree

QEMU documentation can't be opened if QEMU is run from build tree
because executables are placed in the top of build tree after conversion
to meson.

Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: fa56cf7e86f99d5557a4fb730e375777b89d8b50
      
https://github.com/qemu/qemu/commit/fa56cf7e86f99d5557a4fb730e375777b89d8b50
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M docs/meson.build

  Log Message:
  -----------
  docs: Add qemu-storage-daemon(1) manpage to meson.build

In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage.
At the moment new manpages have to be listed both in the conf.py for
Sphinx and also in docs/meson.build for Meson. We forgot the second
of those -- correct the omission.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20210108161416.21129-2-peter.maydell@linaro.org


  Commit: 5e559fd8183caf8327baa20e4c5b1d21a5048b05
      
https://github.com/qemu/qemu/commit/5e559fd8183caf8327baa20e4c5b1d21a5048b05
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M docs/conf.py
    R docs/devel/conf.py
    R docs/index.html.in
    R docs/interop/conf.py
    M docs/meson.build
    R docs/specs/conf.py
    R docs/system/conf.py
    R docs/tools/conf.py
    R docs/user/conf.py

  Log Message:
  -----------
  docs: Build and install all the docs in a single manual

When we first converted our documentation to Sphinx, we split it into
multiple manuals (system, interop, tools, etc), which are all built
separately.  The primary driver for this was wanting to be able to
avoid shipping the 'devel' manual to end-users.  However, this is
working against the grain of the way Sphinx wants to be used and
causes some annoyances:
 * Cross-references between documents become much harder or
   possibly impossible
 * There is no single index to the whole documentation
 * Within one manual there's no links or table-of-contents info
   that lets you easily navigate to the others
 * The devel manual doesn't get published on the QEMU website
   (it would be nice to able to refer to it there)

Merely hiding our developer documentation from end users seems like
it's not enough benefit for these costs.  Combine all the
documentation into a single manual (the same way that the readthedocs
site builds it) and install the whole thing.  The previous manual
divisions remain as the new top level sections in the manual.

 * The per-manual conf.py files are no longer needed
 * The man_pages[] specifications previously in each per-manual
   conf.py move to the top level conf.py
 * docs/meson.build logic is simplified as we now only need to run
   Sphinx once for the HTML and then once for the manpages5B
 * The old index.html.in that produced the top-level page with
   links to each manual is no longer needed

Unfortunately this means that we now have to build the HTML
documentation into docs/manual in the build tree rather than directly
into docs/; otherwise it is too awkward to ensure we install only the
built manual and not also the dependency info, stamp file, etc.  The
manual still ends up in the same place in the final installed
directory, but anybody who was consulting documentation from within
the build tree will have to adjust where they're looking.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20210108161416.21129-3-peter.maydell@linaro.org


  Commit: 6692f0cfad7a5bbe6306679f538187ccdaaabfd9
      
https://github.com/qemu/qemu/commit/6692f0cfad7a5bbe6306679f538187ccdaaabfd9
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns

In commit cd8be50e58f63413c0 we converted the A32 coprocessor
insns to decodetree. This accidentally broke XScale/iWMMXt insns,
because it moved the handling of "cp insns which are handled
by looking up the cp register in the hashtable" from after the
call to the legacy disas_xscale_insn() decode to before it,
with the result that all XScale/iWMMXt insns now UNDEF.

Update valid_cp() so that it knows that on XScale cp 0 and 1
are not standard coprocessor instructions; this will cause
the decodetree trans_ functions to ignore them, so that
execution will correctly get through to the legacy decode again.

Cc: qemu-stable@nongnu.org
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20210108195157.32067-1-peter.maydell@linaro.org


  Commit: 201d085aa7aa0063b3da0ba119bf616b1c138ff1
      
https://github.com/qemu/qemu/commit/201d085aa7aa0063b3da0ba119bf616b1c138ff1
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M hw/net/lan9118.c

  Log Message:
  -----------
  hw/net/lan9118: Fix RX Status FIFO PEEK value

A copy-and-paste error meant that the return value for register offset 0x44
(the RX Status FIFO PEEK register) returned a byte from a bogus offset in
the rx status FIFO. Fix the typo.

Cc: qemu-stable@nongnu.org
Fixes: https://bugs.launchpad.net/qemu/+bug/1904954
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210108180401.2263-2-peter.maydell@linaro.org


  Commit: 16f920b73834838bf0574943a861ebd39200449b
      
https://github.com/qemu/qemu/commit/16f920b73834838bf0574943a861ebd39200449b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M hw/net/lan9118.c

  Log Message:
  -----------
  hw/net/lan9118: Add symbolic constants for register offsets

The lan9118 code mostly uses symbolic constants for register offsets;
the exceptions are those which the datasheet doesn't give an official
symbolic name to.

Add some names for the registers which don't already have them, based
on the longer names they are given in the memory map.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210108180401.2263-3-peter.maydell@linaro.org


  Commit: a79fccd2c4f9d73b5ea48e831b97b8e1cc4bc1fb
      
https://github.com/qemu/qemu/commit/a79fccd2c4f9d73b5ea48e831b97b8e1cc4bc1fb
  Author: Hao Wu <wuhaotsh@google.com>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M hw/misc/npcm7xx_clk.c
    M include/hw/misc/npcm7xx_clk.h

  Log Message:
  -----------
  hw/misc: Add clock converter in NPCM7XX CLK module

This patch allows NPCM7XX CLK module to compute clocks that are used by
other NPCM7XX modules.

Add a new struct NPCM7xxClockConverterState which represents a
single converter.  Each clock converter in CLK module represents one
converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
takes one or more input clocks and converts them into one output clock.
They form a clock hierarchy in the CLK module and are responsible for
outputing clocks for various other modules in an NPCM7XX SoC.

Each converter has a function pointer called "convert" which represents
the unique logic for that converter.

The clock contains two initialization information: ConverterInitInfo and
ConverterConnectionInfo. They represent the vertices and edges in the
clock diagram respectively.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108190945.949196-2-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 157848cf42e6cdf46cc3396b4796b2c96d493cfb
      
https://github.com/qemu/qemu/commit/157848cf42e6cdf46cc3396b4796b2c96d493cfb
  Author: Hao Wu <wuhaotsh@google.com>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M hw/arm/npcm7xx.c
    M hw/timer/npcm7xx_timer.c
    M include/hw/misc/npcm7xx_clk.h
    M include/hw/timer/npcm7xx_timer.h

  Log Message:
  -----------
  hw/timer: Refactor NPCM7XX Timer to use CLK clock

This patch makes NPCM7XX Timer to use a the timer clock generated by the
CLK module instead of the magic number TIMER_REF_HZ.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20210108190945.949196-3-wuhaotsh@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d80125b960de96639632f7993637767f633a2ead
      
https://github.com/qemu/qemu/commit/d80125b960de96639632f7993637767f633a2ead
  Author: Hao Wu <wuhaotsh@google.com>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M docs/system/arm/nuvoton.rst
    M hw/adc/meson.build
    A hw/adc/npcm7xx_adc.c
    A hw/adc/trace-events
    A hw/adc/trace.h
    M hw/arm/npcm7xx.c
    A include/hw/adc/npcm7xx_adc.h
    M include/hw/arm/npcm7xx.h
    M meson.build
    M tests/qtest/meson.build
    A tests/qtest/npcm7xx_adc-test.c

  Log Message:
  -----------
  hw/adc: Add an ADC module for NPCM7XX

The ADC is part of NPCM7XX Module. Its behavior is controled by the
ADC_CON register. It converts one of the eight analog inputs into a
digital input and stores it in the ADC_DATA register when enabled.

Users can alter input value by using qom-set QMP command.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20210108190945.949196-4-wuhaotsh@google.com
[PMM: Added missing hw/adc/trace.h file]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6f1d8b10d051d3d5e4ed99d7e8c922f1d76e1220
      
https://github.com/qemu/qemu/commit/6f1d8b10d051d3d5e4ed99d7e8c922f1d76e1220
  Author: Hao Wu <wuhaotsh@google.com>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M docs/system/arm/nuvoton.rst
    M hw/arm/npcm7xx.c
    M hw/misc/meson.build
    A hw/misc/npcm7xx_pwm.c
    M hw/misc/trace-events
    M include/hw/arm/npcm7xx.h
    A include/hw/misc/npcm7xx_pwm.h

  Log Message:
  -----------
  hw/misc: Add a PWM module for NPCM7XX

The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
identical PWM modules. Each module contains 4 PWM entries. Each PWM has
two outputs: frequency and duty_cycle. Both are computed using inputs
from software side.

This module does not model detail pulse signals since it is expensive.
It also does not model interrupts and watchdogs that are dependant on
the detail models. The interfaces for these are left in the module so
that anyone in need for these functionalities can implement on their
own.

The user can read the duty cycle and frequency using qom-get command.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20210108190945.949196-5-wuhaotsh@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 87a60f5873c07d1b9deb57aa6ae5680b674d0318
      
https://github.com/qemu/qemu/commit/87a60f5873c07d1b9deb57aa6ae5680b674d0318
  Author: Hao Wu <wuhaotsh@google.com>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M tests/qtest/meson.build
    A tests/qtest/npcm7xx_pwm-test.c

  Log Message:
  -----------
  hw/misc: Add QTest for NPCM7XX PWM Module

We add a qtest for the PWM in the previous patch. It proves it works as
expected.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108190945.949196-6-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: eca1d74080baa77bc665c13976f935d77e58a501
      
https://github.com/qemu/qemu/commit/eca1d74080baa77bc665c13976f935d77e58a501
  Author: Hao Wu <wuhaotsh@google.com>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M hw/arm/npcm7xx_boards.c
    M hw/mem/npcm7xx_mc.c
    M hw/misc/npcm7xx_clk.c
    M hw/misc/npcm7xx_gcr.c
    M hw/misc/npcm7xx_rng.c
    M hw/nvram/npcm7xx_otp.c
    M hw/ssi/npcm7xx_fiu.c

  Log Message:
  -----------
  hw/*: Use type casting for SysBusDevice in NPCM7XX

A device shouldn't access its parent object which is QOM internal.
Instead it should use type cast for this purporse. This patch fixes this
issue for all NPCM7XX Devices.

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108190945.949196-7-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 19d131395ccaf503db21dadd8257e6dc9fc1d7de
      
https://github.com/qemu/qemu/commit/19d131395ccaf503db21dadd8257e6dc9fc1d7de
  Author: Roman Bolshakov <r.bolshakov@yadro.com>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M ui/cocoa.m

  Log Message:
  -----------
  ui/cocoa: Fix openFile: deprecation on Big Sur

ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in 
macOS 11.0 - Use -[NSWorkspace openURL:] instead.
      [-Wdeprecated-declarations]
        if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
                                           ^
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1:
 note:
      'openFile:' has been explicitly marked deprecated here
- (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace 
openURL:] instead.", macos(10.0, 11.0));
^

Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7f96aee7ea199e536610b00444ac67c93682dd8c
      
https://github.com/qemu/qemu/commit/7f96aee7ea199e536610b00444ac67c93682dd8c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-01-12 (Tue, 12 Jan 2021)

  Changed paths:
    M docs/conf.py
    R docs/devel/conf.py
    R docs/index.html.in
    R docs/interop/conf.py
    M docs/meson.build
    R docs/specs/conf.py
    M docs/system/arm/nuvoton.rst
    R docs/system/conf.py
    R docs/tools/conf.py
    R docs/user/conf.py
    M hw/adc/meson.build
    A hw/adc/npcm7xx_adc.c
    A hw/adc/trace-events
    A hw/adc/trace.h
    M hw/arm/npcm7xx.c
    M hw/arm/npcm7xx_boards.c
    M hw/mem/npcm7xx_mc.c
    M hw/misc/meson.build
    M hw/misc/npcm7xx_clk.c
    M hw/misc/npcm7xx_gcr.c
    A hw/misc/npcm7xx_pwm.c
    M hw/misc/npcm7xx_rng.c
    M hw/misc/trace-events
    M hw/net/lan9118.c
    M hw/nvram/npcm7xx_otp.c
    M hw/ssi/npcm7xx_fiu.c
    M hw/timer/npcm7xx_timer.c
    A include/hw/adc/npcm7xx_adc.h
    M include/hw/arm/npcm7xx.h
    M include/hw/misc/npcm7xx_clk.h
    A include/hw/misc/npcm7xx_pwm.h
    M include/hw/timer/npcm7xx_timer.h
    M meson.build
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c
    M target/arm/translate.c
    M tests/qtest/meson.build
    A tests/qtest/npcm7xx_adc-test.c
    A tests/qtest/npcm7xx_pwm-test.c
    M ui/cocoa.m

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210112' 
into staging

target-arm queue:
 * arm: Support emulation of ARMv8.4-TTST extension
 * arm: Update cpu.h ID register field definitions
 * arm: Fix breakage of XScale instruction emulation
 * hw/net/lan9118: Fix RX Status FIFO PEEK value
 * npcm7xx: Add ADC and PWM emulation
 * ui/cocoa: Make "open docs" help menu entry work again when binary
   is run from the build tree
 * ui/cocoa: Fix openFile: deprecation on Big Sur
 * docs: Add qemu-storage-daemon(1) manpage to meson.build
 * docs: Build and install all the docs in a single manual

# gpg: Signature made Tue 12 Jan 2021 16:56:27 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210112: (21 commits)
  ui/cocoa: Fix openFile: deprecation on Big Sur
  hw/*: Use type casting for SysBusDevice in NPCM7XX
  hw/misc: Add QTest for NPCM7XX PWM Module
  hw/misc: Add a PWM module for NPCM7XX
  hw/adc: Add an ADC module for NPCM7XX
  hw/timer: Refactor NPCM7XX Timer to use CLK clock
  hw/misc: Add clock converter in NPCM7XX CLK module
  hw/net/lan9118: Add symbolic constants for register offsets
  hw/net/lan9118: Fix RX Status FIFO PEEK value
  target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
  docs: Build and install all the docs in a single manual
  docs: Add qemu-storage-daemon(1) manpage to meson.build
  ui/cocoa: Update path to docs in build tree
  target/arm: add aarch32 ID register fields to cpu.h
  target/arm: add aarch64 ID register fields to cpu.h
  target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
  target/arm: make ARMCPU.ctr 64-bit
  target/arm: make ARMCPU.clidr 64-bit
  target/arm: fix typo in cpu.h ID_AA64PFR1 field name
  target/arm: enable Small Translation tables in max CPU
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


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