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[Qemu-commits] [qemu/qemu] c51a3f: target/riscv: Fix bug in getting trap
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] c51a3f: target/riscv: Fix bug in getting trap cause name f... |
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Date: |
Sun, 13 Sep 2020 14:31:14 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: c51a3f5d155b66b190192fcba49c52eb30c9eaab
https://github.com/qemu/qemu/commit/c51a3f5d155b66b190192fcba49c52eb30c9eaab
Author: Yifei Jiang <jiangyifei@huawei.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Fix bug in getting trap cause name for trace_riscv_trap
When the cause number is equal to or greater than 23, print "(unknown)" in
trace_riscv_trap. The max valid number of riscv_excp_names is 23, so the last
excpetion "guest_store_page_fault" can not be printed.
In addition, the current check of cause is invalid for riscv_intr_names. So
introduce riscv_cpu_get_trap_name to get the trap cause name.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200814035819.1214-1-jiangyifei@huawei.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ab3d207fe89bc0c63739db19e177af49179aa457
https://github.com/qemu/qemu/commit/ab3d207fe89bc0c63739db19e177af49179aa457
Author: Nathan Chancellor <natechancellor@gmail.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/riscv/sifive_test.c
Log Message:
-----------
riscv: sifive_test: Allow 16-bit writes to memory region
When shutting down the machine running a mainline Linux kernel, the
following error happens:
$ build/riscv64-softmmu/qemu-system-riscv64 -bios default -M virt \
-display none -initrd rootfs.cpio -kernel Image -m 512m \
-nodefaults -serial mon:stdio
...
Requesting system poweroff
[ 4.999630] reboot: Power down
sbi_trap_error: hart0: trap handler failed (error -2)
sbi_trap_error: hart0: mcause=0x0000000000000007 mtval=0x0000000000100000
sbi_trap_error: hart0: mepc=0x000000008000d4cc mstatus=0x0000000000001822
sbi_trap_error: hart0: ra=0x000000008000999e sp=0x0000000080015c78
sbi_trap_error: hart0: gp=0xffffffe000e76610 tp=0xffffffe0081b89c0
sbi_trap_error: hart0: s0=0x0000000080015c88 s1=0x0000000000000040
sbi_trap_error: hart0: a0=0x0000000000000000 a1=0x0000000080004024
sbi_trap_error: hart0: a2=0x0000000080004024 a3=0x0000000080004024
sbi_trap_error: hart0: a4=0x0000000000100000 a5=0x0000000000005555
sbi_trap_error: hart0: a6=0x0000000000004024 a7=0x0000000080011158
sbi_trap_error: hart0: s2=0x0000000000000000 s3=0x0000000080016000
sbi_trap_error: hart0: s4=0x0000000000000000 s5=0x0000000000000000
sbi_trap_error: hart0: s6=0x0000000000000001 s7=0x0000000000000000
sbi_trap_error: hart0: s8=0x0000000000000000 s9=0x0000000000000000
sbi_trap_error: hart0: s10=0x0000000000000000 s11=0x0000000000000008
sbi_trap_error: hart0: t0=0x0000000000000000 t1=0x0000000000000000
sbi_trap_error: hart0: t2=0x0000000000000000 t3=0x0000000000000000
sbi_trap_error: hart0: t4=0x0000000000000000 t5=0x0000000000000000
sbi_trap_error: hart0: t6=0x0000000000000000
The kernel does a 16-bit write when powering off the machine, which
was allowed before commit 5d971f9e67 ("memory: Revert "memory: accept
mismatching sizes in memory_region_access_valid""). Make min_access_size
match reality so that the machine can shut down properly now.
Cc: qemu-stable@nongnu.org
Fixes: 88a07990fa ("SiFive RISC-V Test Finisher")
Fixes: 5d971f9e67 ("memory: Revert "memory: accept mismatching sizes in
memory_region_access_valid"")
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200901055822.2721209-1-natechancellor@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9b4c9b2b2a50fe4eb90d0ac2d8723b46ecb42511
https://github.com/qemu/qemu/commit/9b4c9b2b2a50fe4eb90d0ac2d8723b46ecb42511
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: cpu: Add a new 'resetvec' property
Currently the reset vector address is hard-coded in a RISC-V CPU's
instance_init() routine. In a real world we can have 2 exact same
CPUs except for the reset vector address, which is pretty common in
the RISC-V core IP licensing business.
Normally reset vector address is a configurable parameter. Let's
create a 64-bit property to store the reset vector address which
covers both 32-bit and 64-bit CPUs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4100d5e6dc28cdd89d3eec6e4ddeb9d1a159c330
https://github.com/qemu/qemu/commit/4100d5e6dc28cdd89d3eec6e4ddeb9d1a159c330
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/riscv/riscv_hart.c
M include/hw/riscv/riscv_hart.h
Log Message:
-----------
hw/riscv: hart: Add a new 'resetvec' property
RISC-V machines do not instantiate RISC-V CPUs directly, instead
they do that via the hart array. Add a new property for the reset
vector address to allow the value to be passed to the CPU, before
CPU is realized.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 73f6ed97acdbf7aec72d368fd5e16c00e04ac172
https://github.com/qemu/qemu/commit/73f6ed97acdbf7aec72d368fd5e16c00e04ac172
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/riscv/opentitan.c
M hw/riscv/sifive_e.c
M hw/riscv/sifive_u.c
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: cpu: Set reset vector based on the configured property value
Now that we have the newly introduced 'resetvec' property in the
RISC-V CPU and HART, instead of hard-coding the reset vector addr
in the CPU's instance_init(), move that to riscv_cpu_realize()
based on the configured property value from the RISC-V machines.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 56f6e31e7b7e06a66a0efd5464fa4257de7ec242
https://github.com/qemu/qemu/commit/56f6e31e7b7e06a66a0efd5464fa4257de7ec242
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M MAINTAINERS
M default-configs/riscv64-softmmu.mak
M hw/riscv/Kconfig
M hw/riscv/meson.build
A hw/riscv/microchip_pfsoc.c
A include/hw/riscv/microchip_pfsoc.h
Log Message:
-----------
hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
This is an initial support for Microchip PolarFire SoC Icicle Kit.
The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
E51 plus four U54 cores and many on-chip peripherals and an FPGA.
For more details about Microchip PolarFire Soc, please see:
https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000.
The following perepherals are created as an unimplemented device:
- Bus Error Uint 0/1/2/3/4
- L2 cache controller
- SYSREG
- MPUCFG
- IOSCBCFG
More devices will be added later.
The BIOS image used by this machine is hss.bin, aka Hart Software
Services, which can be built from:
https://github.com/polarfire-soc/hart-software-services
To launch this machine:
$ qemu-system-riscv64 -nographic -M microchip-icicle-kit
The memory is set to 1 GiB by default to match the hardware.
A sanity check on ram size is performed in the machine init routine
to prompt user to increase the RAM size to > 1 GiB when less than
1 GiB ram is detected.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a8fb0a500a695104cda5837b7aba93dee3abddde
https://github.com/qemu/qemu/commit/a8fb0a500a695104cda5837b7aba93dee3abddde
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M MAINTAINERS
M hw/char/Kconfig
A hw/char/mchp_pfsoc_mmuart.c
M hw/char/meson.build
A include/hw/char/mchp_pfsoc_mmuart.h
Log Message:
-----------
hw/char: Add Microchip PolarFire SoC MMUART emulation
Microchip PolarFire SoC MMUART is ns16550 compatible, with some
additional registers. Create a simple MMUART model built on top
of the existing ns16550 model.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8f2ac39d5d307589faca1d00d55a1a8054d53b0e
https://github.com/qemu/qemu/commit/8f2ac39d5d307589faca1d00d55a1a8054d53b0e
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/riscv/Kconfig
M hw/riscv/microchip_pfsoc.c
M include/hw/riscv/microchip_pfsoc.h
Log Message:
-----------
hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board
wires 4 of them out. Let's connect all 5 MMUARTs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-7-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c696e1f2b392af19653e82da26df3c61b85ab5a2
https://github.com/qemu/qemu/commit/c696e1f2b392af19653e82da26df3c61b85ab5a2
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/sd/Kconfig
A hw/sd/cadence_sdhci.c
M hw/sd/meson.build
A include/hw/sd/cadence_sdhci.h
Log Message:
-----------
hw/sd: Add Cadence SDHCI emulation
Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
controller. The SDHCI compatible registers start from offset 0x200,
which are called Slot Register Set (SRS) in its datasheet.
This creates a Cadence SDHCI model built on top of the existing
generic SDHCI model. Cadence specific Host Register Set (HRS) is
implemented to make guest software happy.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 898dc008e8cd474c21f98a63f151265673aea305
https://github.com/qemu/qemu/commit/898dc008e8cd474c21f98a63f151265673aea305
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/riscv/Kconfig
M hw/riscv/microchip_pfsoc.c
M include/hw/riscv/microchip_pfsoc.h
Log Message:
-----------
hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card
Microchip PolarFire SoC integrates one Cadence SDHCI controller.
On the Icicle Kit board, one eMMC chip and an external SD card
connect to this controller depending on different configuration.
As QEMU does not support eMMC yet, we just emulate the SD card
configuration. To test this, the Hart Software Services (HSS)
should choose the SD card configuration:
$ cp boards/icicle-kit-es/def_config.sdcard .config
$ make BOARD=icicle-kit-es
The SD card image can be built from the Yocto BSP at:
https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp
Note the generated SD card image should be resized before use:
$ qemu-img resize /path/to/sdcard.img 4G
Launch QEMU with the following command:
$ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 97ba42230b28636e02ab0af77738bb247e051dd4
https://github.com/qemu/qemu/commit/97ba42230b28636e02ab0af77738bb247e051dd4
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/dma/Kconfig
M hw/dma/meson.build
A hw/dma/sifive_pdma.c
A include/hw/dma/sifive_pdma.h
Log Message:
-----------
hw/dma: Add SiFive platform DMA controller emulation
Microchip PolarFire SoC integrates a DMA engine that supports:
* Independent concurrent DMA transfers using 4 DMA channels
* Generation of interrupts on various conditions during execution
which is actually an IP reused from the SiFive FU540 chip.
This creates a model to support both polling and interrupt modes.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-10-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7124e27bb8ac16b6aae0e9cd30fb19385430dbb5
https://github.com/qemu/qemu/commit/7124e27bb8ac16b6aae0e9cd30fb19385430dbb5
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/riscv/Kconfig
M hw/riscv/microchip_pfsoc.c
M include/hw/riscv/microchip_pfsoc.h
Log Message:
-----------
hw/riscv: microchip_pfsoc: Connect a DMA controller
On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA
controller to move the 2nd stage bootloader in the system memory.
Let's connect a DMA controller to Microchip PolarFire SoC.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-11-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 64ac13633fd416541ea00ff4ae973489bdc33f7a
https://github.com/qemu/qemu/commit/64ac13633fd416541ea00ff4ae973489bdc33f7a
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/net/cadence_gem.c
M include/hw/net/cadence_gem.h
Log Message:
-----------
hw/net: cadence_gem: Add a new 'phy-addr' property
At present the PHY address of the PHY connected to GEM is hard-coded
to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for
all boards. Add a new 'phy-addr' property so that board can specify
the PHY address for each GEM instance.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-12-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: dfc388797cc413072e58a8f9a831633f29212448
https://github.com/qemu/qemu/commit/dfc388797cc413072e58a8f9a831633f29212448
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/arm/xilinx_zynq.c
M hw/arm/xlnx-versal.c
M hw/arm/xlnx-zynqmp.c
M hw/net/cadence_gem.c
Log Message:
-----------
hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
When cadence_gem model was created for Xilinx boards, the PHY address
was hard-coded to 23 in the GEM model. Now that we have introduced a
property we can use that to tell GEM model what our PHY address is.
Change all boards' GEM 'phy-addr' property value to 23, and set the
PHY address default value to 0 in the GEM model.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-13-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 47374b0761c1e3b6bff210dbb9d1a965e71c213e
https://github.com/qemu/qemu/commit/47374b0761c1e3b6bff210dbb9d1a965e71c213e
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/riscv/microchip_pfsoc.c
M include/hw/riscv/microchip_pfsoc.h
Log Message:
-----------
hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
Microchip PolarFire SoC integrates 2 Candence GEMs to provide
IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface.
On the Icicle Kit board, GEM0 connects to a PHY at address 8 while
GEM1 connects to a PHY at address 9.
The 2nd stage bootloader (U-Boot) is using GEM1 by default, so we
must specify 2 '-nic' options from the command line in order to get
a working ethernet.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-14-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ce908a2f6f6d6e1d8ede485ee3f9f7d36ee3533c
https://github.com/qemu/qemu/commit/ce908a2f6f6d6e1d8ede485ee3f9f7d36ee3533c
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/riscv/microchip_pfsoc.c
M include/hw/riscv/microchip_pfsoc.h
Log Message:
-----------
hw/riscv: microchip_pfsoc: Hook GPIO controllers
Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems
enough to create unimplemented devices to cover their register
spaces at this point.
With this commit, QEMU can boot to U-Boot (2nd stage bootloader)
all the way to the Linux shell login prompt, with a modified HSS
(1st stage bootloader).
For detailed instructions on how to create images for the Icicle
Kit board, please check QEMU RISC-V WiKi page at:
https://wiki.qemu.org/Documentation/Platforms/RISCV
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-15-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a47ef6e93ab2ca1db8d5ecb61fda3c41f926a26b
https://github.com/qemu/qemu/commit/a47ef6e93ab2ca1db8d5ecb61fda3c41f926a26b
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/riscv/microchip_pfsoc.c
M hw/riscv/sifive_clint.c
M hw/riscv/sifive_e.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/riscv/sifive_clint.h
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
Log Message:
-----------
hw/riscv: clint: Avoid using hard-coded timebase frequency
At present the CLINT timestamp is using a hard-coded timebase
frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be
true for all boards.
Add a new 'timebase-freq' property to the CLINT device, and
update various functions to accept this as a parameter.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-16-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 834e027a3452e1c139c5400cae550c6c5a340b28
https://github.com/qemu/qemu/commit/834e027a3452e1c139c5400cae550c6c5a340b28
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/riscv/Kconfig
M hw/riscv/sifive_u.c
M include/hw/riscv/sifive_u.h
Log Message:
-----------
hw/riscv: sifive_u: Connect a DMA controller
SiFive FU540 SoC integrates a platform DMA controller with 4 DMA
channels. This connects the exsiting SiFive PDMA model to the SoC,
and adds its device tree data as well.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-17-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 89ece6f76f089bc415fc4b8c78f7dbe74113380c
https://github.com/qemu/qemu/commit/89ece6f76f089bc415fc4b8c78f7dbe74113380c
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/sifive_e_prci.c
M hw/riscv/Kconfig
M hw/riscv/meson.build
M hw/riscv/sifive_e.c
R hw/riscv/sifive_e_prci.c
A include/hw/misc/sifive_e_prci.h
R include/hw/riscv/sifive_e_prci.h
Log Message:
-----------
hw/riscv: Move sifive_e_prci model to hw/misc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_e_prci model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9fe640a53dd8ef33d32ab6e833fa9b6d1356cfae
https://github.com/qemu/qemu/commit/9fe640a53dd8ef33d32ab6e833fa9b6d1356cfae
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/sifive_u_prci.c
M hw/riscv/Kconfig
M hw/riscv/meson.build
R hw/riscv/sifive_u_prci.c
A include/hw/misc/sifive_u_prci.h
M include/hw/riscv/sifive_u.h
R include/hw/riscv/sifive_u_prci.h
Log Message:
-----------
hw/riscv: Move sifive_u_prci model to hw/misc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_prci model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0fa9e329454aaccc6dbb6a4f52ad0c88a060a3b6
https://github.com/qemu/qemu/commit/0fa9e329454aaccc6dbb6a4f52ad0c88a060a3b6
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/sifive_u_otp.c
M hw/riscv/Kconfig
M hw/riscv/meson.build
R hw/riscv/sifive_u_otp.c
A include/hw/misc/sifive_u_otp.h
M include/hw/riscv/sifive_u.h
R include/hw/riscv/sifive_u_otp.h
Log Message:
-----------
hw/riscv: Move sifive_u_otp model to hw/misc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_otp model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4921a0ce86cecd03e6918832673db79de62e6fe1
https://github.com/qemu/qemu/commit/4921a0ce86cecd03e6918832673db79de62e6fe1
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/gpio/Kconfig
M hw/gpio/meson.build
A hw/gpio/sifive_gpio.c
M hw/gpio/trace-events
M hw/riscv/Kconfig
M hw/riscv/meson.build
R hw/riscv/sifive_gpio.c
R hw/riscv/trace-events
R hw/riscv/trace.h
A include/hw/gpio/sifive_gpio.h
M include/hw/riscv/sifive_e.h
R include/hw/riscv/sifive_gpio.h
M include/hw/riscv/sifive_u.h
M meson.build
Log Message:
-----------
hw/riscv: Move sifive_gpio model to hw/gpio
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_gpio model to hw/gpio directory.
Note this also removes the trace-events in the hw/riscv directory,
since gpio is the only supported trace target in that directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 406fafd5d0f9a1c6a365ff1733c26a043b1c4877
https://github.com/qemu/qemu/commit/406fafd5d0f9a1c6a365ff1733c26a043b1c4877
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/intc/Kconfig
M hw/intc/meson.build
A hw/intc/sifive_clint.c
M hw/riscv/Kconfig
M hw/riscv/meson.build
M hw/riscv/microchip_pfsoc.c
R hw/riscv/sifive_clint.c
M hw/riscv/sifive_e.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
A include/hw/intc/sifive_clint.h
R include/hw/riscv/sifive_clint.h
Log Message:
-----------
hw/riscv: Move sifive_clint model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_clint model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 84fcf3c15111de9f0c72efbb6bc0def264555c46
https://github.com/qemu/qemu/commit/84fcf3c15111de9f0c72efbb6bc0def264555c46
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/intc/Kconfig
M hw/intc/meson.build
A hw/intc/sifive_plic.c
A hw/intc/sifive_plic.h
M hw/riscv/Kconfig
M hw/riscv/meson.build
M hw/riscv/microchip_pfsoc.c
M hw/riscv/sifive_e.c
R hw/riscv/sifive_plic.c
M hw/riscv/sifive_u.c
M hw/riscv/virt.c
R include/hw/riscv/sifive_plic.h
Log Message:
-----------
hw/riscv: Move sifive_plic model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_plic model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 70eb9f9cd1c0b519b31df8ab08ee2198b0e16176
https://github.com/qemu/qemu/commit/70eb9f9cd1c0b519b31df8ab08ee2198b0e16176
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/char/Kconfig
M hw/char/meson.build
A hw/char/riscv_htif.c
M hw/riscv/Kconfig
M hw/riscv/meson.build
R hw/riscv/riscv_htif.c
M hw/riscv/spike.c
A include/hw/char/riscv_htif.h
R include/hw/riscv/riscv_htif.h
Log Message:
-----------
hw/riscv: Move riscv_htif model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move riscv_htif model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-8-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b609b7e3199912e16ef3b0447823f21fed73597e
https://github.com/qemu/qemu/commit/b609b7e3199912e16ef3b0447823f21fed73597e
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/char/Kconfig
M hw/char/meson.build
A hw/char/sifive_uart.c
M hw/riscv/Kconfig
M hw/riscv/meson.build
M hw/riscv/sifive_e.c
M hw/riscv/sifive_u.c
R hw/riscv/sifive_uart.c
A include/hw/char/sifive_uart.h
R include/hw/riscv/sifive_uart.h
Log Message:
-----------
hw/riscv: Move sifive_uart model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a4b84608ba0eecce1d4858181457dc26582e6d28
https://github.com/qemu/qemu/commit/a4b84608ba0eecce1d4858181457dc26582e6d28
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/sifive_test.c
M hw/riscv/Kconfig
M hw/riscv/meson.build
R hw/riscv/sifive_test.c
M hw/riscv/virt.c
A include/hw/misc/sifive_test.h
R include/hw/riscv/sifive_test.h
Log Message:
-----------
hw/riscv: Move sifive_test model to hw/misc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_test model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-10-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 30a4af1664aa0effdde8db18c92113653befdbdd
https://github.com/qemu/qemu/commit/30a4af1664aa0effdde8db18c92113653befdbdd
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/riscv/Kconfig
M hw/riscv/meson.build
Log Message:
-----------
hw/riscv: Always build riscv_hart.c
Every RISC-V machine needs riscv_hart hence there is no need to
have a dedicated Kconfig option for it. Drop the Kconfig option
and always build riscv_hart.c.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-11-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4791b4c4abc858b9726d4670fa08d37d73cf7d32
https://github.com/qemu/qemu/commit/4791b4c4abc858b9726d4670fa08d37d73cf7d32
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/riscv/Kconfig
Log Message:
-----------
hw/riscv: Drop CONFIG_SIFIVE
The name SIFIVE is too vague to convey the required component of
MSI_NONBROKEN. Let's drop the option, and select MSI_NONBROKEN in
each machine instead.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-12-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7595a65818ea9b49c36650a8c217a1ef9bd6e62a
https://github.com/qemu/qemu/commit/7595a65818ea9b49c36650a8c217a1ef9bd6e62a
Author: Bin Meng <bin.meng@windriver.com>
Date: 2020-09-09 (Wed, 09 Sep 2020)
Changed paths:
M hw/riscv/Kconfig
Log Message:
-----------
hw/riscv: Sort the Kconfig options in alphabetical order
At present the Kconfig file is in disorder. Let's sort the options.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-13-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f00f57f344236bbbe4c20845a0276a490dd5ffea
https://github.com/qemu/qemu/commit/f00f57f344236bbbe4c20845a0276a490dd5ffea
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-09-13 (Sun, 13 Sep 2020)
Changed paths:
M MAINTAINERS
M default-configs/riscv64-softmmu.mak
M hw/arm/xilinx_zynq.c
M hw/arm/xlnx-versal.c
M hw/arm/xlnx-zynqmp.c
M hw/char/Kconfig
A hw/char/mchp_pfsoc_mmuart.c
M hw/char/meson.build
A hw/char/riscv_htif.c
A hw/char/sifive_uart.c
M hw/dma/Kconfig
M hw/dma/meson.build
A hw/dma/sifive_pdma.c
M hw/gpio/Kconfig
M hw/gpio/meson.build
A hw/gpio/sifive_gpio.c
M hw/gpio/trace-events
M hw/intc/Kconfig
M hw/intc/meson.build
A hw/intc/sifive_clint.c
A hw/intc/sifive_plic.c
A hw/intc/sifive_plic.h
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/sifive_e_prci.c
A hw/misc/sifive_test.c
A hw/misc/sifive_u_otp.c
A hw/misc/sifive_u_prci.c
M hw/net/cadence_gem.c
M hw/riscv/Kconfig
M hw/riscv/meson.build
A hw/riscv/microchip_pfsoc.c
M hw/riscv/opentitan.c
M hw/riscv/riscv_hart.c
R hw/riscv/riscv_htif.c
R hw/riscv/sifive_clint.c
M hw/riscv/sifive_e.c
R hw/riscv/sifive_e_prci.c
R hw/riscv/sifive_gpio.c
R hw/riscv/sifive_plic.c
R hw/riscv/sifive_test.c
M hw/riscv/sifive_u.c
R hw/riscv/sifive_u_otp.c
R hw/riscv/sifive_u_prci.c
R hw/riscv/sifive_uart.c
M hw/riscv/spike.c
R hw/riscv/trace-events
R hw/riscv/trace.h
M hw/riscv/virt.c
M hw/sd/Kconfig
A hw/sd/cadence_sdhci.c
M hw/sd/meson.build
A include/hw/char/mchp_pfsoc_mmuart.h
A include/hw/char/riscv_htif.h
A include/hw/char/sifive_uart.h
A include/hw/dma/sifive_pdma.h
A include/hw/gpio/sifive_gpio.h
A include/hw/intc/sifive_clint.h
A include/hw/misc/sifive_e_prci.h
A include/hw/misc/sifive_test.h
A include/hw/misc/sifive_u_otp.h
A include/hw/misc/sifive_u_prci.h
M include/hw/net/cadence_gem.h
A include/hw/riscv/microchip_pfsoc.h
M include/hw/riscv/riscv_hart.h
R include/hw/riscv/riscv_htif.h
R include/hw/riscv/sifive_clint.h
M include/hw/riscv/sifive_e.h
R include/hw/riscv/sifive_e_prci.h
R include/hw/riscv/sifive_gpio.h
R include/hw/riscv/sifive_plic.h
R include/hw/riscv/sifive_test.h
M include/hw/riscv/sifive_u.h
R include/hw/riscv/sifive_u_otp.h
R include/hw/riscv/sifive_u_prci.h
R include/hw/riscv/sifive_uart.h
A include/hw/sd/cadence_sdhci.h
M meson.build
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging
This PR includes multiple fixes and features for RISC-V:
- Fixes a bug in printing trap causes
- Allows 16-bit writes to the SiFive test device. This fixes the
failure to reboot the RISC-V virt machine
- Support for the Microchip PolarFire SoC and Icicle Kit
- A reafactor of RISC-V code out of hw/riscv
# gpg: Signature made Thu 10 Sep 2020 19:08:06 BST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits)
hw/riscv: Sort the Kconfig options in alphabetical order
hw/riscv: Drop CONFIG_SIFIVE
hw/riscv: Always build riscv_hart.c
hw/riscv: Move sifive_test model to hw/misc
hw/riscv: Move sifive_uart model to hw/char
hw/riscv: Move riscv_htif model to hw/char
hw/riscv: Move sifive_plic model to hw/intc
hw/riscv: Move sifive_clint model to hw/intc
hw/riscv: Move sifive_gpio model to hw/gpio
hw/riscv: Move sifive_u_otp model to hw/misc
hw/riscv: Move sifive_u_prci model to hw/misc
hw/riscv: Move sifive_e_prci model to hw/misc
hw/riscv: sifive_u: Connect a DMA controller
hw/riscv: clint: Avoid using hard-coded timebase frequency
hw/riscv: microchip_pfsoc: Hook GPIO controllers
hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
hw/net: cadence_gem: Add a new 'phy-addr' property
hw/riscv: microchip_pfsoc: Connect a DMA controller
hw/dma: Add SiFive platform DMA controller emulation
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts:
# hw/riscv/trace-events
Compare: https://github.com/qemu/qemu/compare/3d9f371b0106...f00f57f34423
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Peter Maydell <=