[Qemu-commits] [qemu/qemu] dac717: dma/xlnx-zdma: Fix descriptor loading (MEM) wrt en...

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: dac717da679938d52be05c8232cd818e7902796c
      
https://github.com/qemu/qemu/commit/dac717da679938d52be05c8232cd818e7902796c
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/dma/xlnx-zdma.c

  Log Message:
  -----------
  dma/xlnx-zdma: Fix descriptor loading (MEM) wrt endianness

Fix descriptor loading from memory wrt host endianness.

Reported-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Francisco Iglesias <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1633ed1e2de68cc27a1be8ff2a63e09c37e592f5
      
https://github.com/qemu/qemu/commit/1633ed1e2de68cc27a1be8ff2a63e09c37e592f5
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/dma/xlnx-zdma.c

  Log Message:
  -----------
  dma/xlnx-zdma: Fix descriptor loading (REG) wrt endianness

Fix descriptor loading from registers wrt host endianness.

Reported-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Francisco Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c8aeef3aed6beef14175f9c6744b2ea30fc309d9
      
https://github.com/qemu/qemu/commit/c8aeef3aed6beef14175f9c6744b2ea30fc309d9
  Author: Cameron Esfahani <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M include/hw/gpio/nrf51_gpio.h

  Log Message:
  -----------
  nrf51: Fix last GPIO CNF address

NRF51_GPIO_REG_CNF_END doesn't actually refer to the start of the last
valid CNF register: it's referring to the last byte of the last valid
CNF register.

This hasn't been a problem up to now, as current implementation in
memory.c turns an unaligned 4-byte read from 0x77f to a single byte read
and the qtest only looks at the least-significant byte of the register.

But when running with patches which fix unaligned accesses in memory.c,
the qtest breaks.

Considering NRF51 doesn't support unaligned accesses, the simplest fix
is to actually set NRF51_GPIO_REG_CNF_END to the start of the last valid
CNF register: 0x77c.

Now, qtests work with or without the unaligned access patches.

Reviewed-by: Cédric Le Goater <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Signed-off-by: Cameron Esfahani <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1e11a139bfed55cb2de7b2eaa1e53f3cf6180d13
      
https://github.com/qemu/qemu/commit/1e11a139bfed55cb2de7b2eaa1e53f3cf6180d13
  Author: Keqian Zhu <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/intc/arm_gicv3_kvm.c

  Log Message:
  -----------
  bugfix: Use gicr_typer in arm_gicv3_icc_reset

The KVM_VGIC_ATTR macro expect the second parameter as gicr_typer,
of which high 32bit is constructed by mp_affinity. For most case,
the high 32bit of mp_affinity is zero, so it will always access the
ICC_CTLR_EL1 of CPU0.

Signed-off-by: Keqian Zhu <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 119a2ef1dce90ffa2b86a43fb190027fcc5cdb9a
      
https://github.com/qemu/qemu/commit/119a2ef1dce90ffa2b86a43fb190027fcc5cdb9a
  Author: Keqian Zhu <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/acpi/cpu.c

  Log Message:
  -----------
  Typo: Correct the name of CPU hotplug memory region

Replace "acpi-mem-hotplug" with "acpi-cpu-hotplug"

Signed-off-by: Keqian Zhu <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1c66437879654705bbf8099d9767594668c57ce8
      
https://github.com/qemu/qemu/commit/1c66437879654705bbf8099d9767594668c57ce8
  Author: Subbaraya Sundeep <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M MAINTAINERS
    M hw/net/Makefile.objs
    A hw/net/msf2-emac.c
    A include/hw/net/msf2-emac.h

  Log Message:
  -----------
  hw/net: Add Smartfusion2 emac block

Modelled Ethernet MAC of Smartfusion2 SoC.
Micrel KSZ8051 PHY is present on Emcraft's
SOM kit hence same PHY is emulated.

Signed-off-by: Subbaraya Sundeep <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 05b7374a58cd18aa3516e33513808896d0ac9b7b
      
https://github.com/qemu/qemu/commit/05b7374a58cd18aa3516e33513808896d0ac9b7b
  Author: Subbaraya Sundeep <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/arm/msf2-soc.c
    M include/hw/arm/msf2-soc.h

  Log Message:
  -----------
  msf2: Add EMAC block to SmartFusion2 SoC

With SmartFusion2 Ethernet MAC model in
place this patch adds the same to SoC.

Signed-off-by: Subbaraya Sundeep <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 70d7857f935ab3fd6a5c0ff8b7586d0aef20f8b0
      
https://github.com/qemu/qemu/commit/70d7857f935ab3fd6a5c0ff8b7586d0aef20f8b0
  Author: Subbaraya Sundeep <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M tests/acceptance/boot_linux_console.py

  Log Message:
  -----------
  tests/boot_linux_console: Add ethernet test to SmartFusion2

In addition to simple serial test this patch uses ping
to test the ethernet block modelled in SmartFusion2 SoC.

Signed-off-by: Subbaraya Sundeep <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4cba075efedde66f0a8658001da7fc09a09024e1
      
https://github.com/qemu/qemu/commit/4cba075efedde66f0a8658001da7fc09a09024e1
  Author: Peter Maydell <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/core/Makefile.objs
    A hw/core/clock.c
    M hw/core/trace-events
    A include/hw/clock.h

  Log Message:
  -----------
  hw/core/clock: introduce clock object

This object may be used to represent a clock inside a clock tree.

A clock may be connected to another clock so that it receives update,
through a callback, whenever the source/parent clock is updated.

Although only the root clock of a clock tree controls the values
(represented as periods) of all clocks in tree, each clock holds
a local state containing the current value so that it can be fetched
independently. It will allows us to fullfill migration requirements
by migrating each clock independently of others.

This is based on the original work of Frederic Konrad.

Signed-off-by: Damien Hedde <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
[PMM: Use uint64_t rather than unsigned long long in trace events;
 the dtrace backend can't handle the latter]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b8d38bd5256362355cbc115889213e4892e16ea9
      
https://github.com/qemu/qemu/commit/b8d38bd5256362355cbc115889213e4892e16ea9
  Author: Damien Hedde <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/core/Makefile.objs
    A hw/core/clock-vmstate.c
    M include/hw/clock.h

  Log Message:
  -----------
  hw/core/clock-vmstate: define a vmstate entry for clock state

Signed-off-by: Damien Hedde <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0e6934f26484abef4a96946078a34746f8855801
      
https://github.com/qemu/qemu/commit/0e6934f26484abef4a96946078a34746f8855801
  Author: Damien Hedde <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/core/Makefile.objs
    A hw/core/qdev-clock.c
    M hw/core/qdev.c
    A include/hw/qdev-clock.h
    M include/hw/qdev-core.h
    M tests/Makefile.include

  Log Message:
  -----------
  qdev: add clock input&output support to devices.

Add functions to easily handle clocks with devices.
Clock inputs and outputs should be used to handle clock propagation
between devices.
The API is very similar the GPIO API.

This is based on the original work of Frederic Konrad.

Signed-off-by: Damien Hedde <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f0bc2a64c08b94e1333b0a210f19f1a43bd2f412
      
https://github.com/qemu/qemu/commit/f0bc2a64c08b94e1333b0a210f19f1a43bd2f412
  Author: Damien Hedde <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/core/qdev-clock.c
    M include/hw/qdev-clock.h

  Log Message:
  -----------
  qdev-clock: introduce an init array to ease the device construction

Introduce a function and macro helpers to setup several clocks
in a device from a static array description.

An element of the array describes the clock (name and direction) as
well as the related callback and an optional offset to store the
created object pointer in the device state structure.

The array must be terminated by a special element QDEV_CLOCK_END.

This is based on the original work of Frederic Konrad.

Signed-off-by: Damien Hedde <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 31e5784a0d822269dc2674495f9f17e3ee0fb68f
      
https://github.com/qemu/qemu/commit/31e5784a0d822269dc2674495f9f17e3ee0fb68f
  Author: Peter Maydell <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    A docs/devel/clocks.rst
    M docs/devel/index.rst

  Log Message:
  -----------
  docs/clocks: add device's clock documentation

Add the documentation about the clock inputs and outputs in devices.

This is based on the original work of Frederic Konrad.

Signed-off-by: Damien Hedde <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
[PMM: Editing pass for minor grammar, style and Sphinx
 formatting fixes]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 38867cb7ec90253289cab22c13282a3ef6530f69
      
https://github.com/qemu/qemu/commit/38867cb7ec90253289cab22c13282a3ef6530f69
  Author: Damien Hedde <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/misc/zynq_slcr.c

  Log Message:
  -----------
  hw/misc/zynq_slcr: add clock generation for uarts

Add some clocks to zynq_slcr
+ the main input clock (ps_clk)
+ the reference clock outputs for each uart (uart0 & 1)

This commit also transitional the slcr to multi-phase reset as it is
required to initialize the clocks correctly.

The clock frequencies are computed using the internal pll & uart configuration
registers and the input ps_clk frequency.

Signed-off-by: Damien Hedde <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b636db306e06ee1c267d6e15e3b5bc109252617f
      
https://github.com/qemu/qemu/commit/b636db306e06ee1c267d6e15e3b5bc109252617f
  Author: Damien Hedde <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/char/cadence_uart.c
    M hw/char/trace-events
    M include/hw/char/cadence_uart.h

  Log Message:
  -----------
  hw/char/cadence_uart: add clock support

Switch the cadence uart to multi-phase reset and add the
reference clock input.

The input clock frequency is added to the migration structure.

The reference clock controls the baudrate generation. If it disabled,
any input characters and events are ignored.

If this clock remains unconnected, the uart behaves as before
(it default to a 50MHz ref clock).

Signed-off-by: Damien Hedde <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5b49a34c6800d0cb917f959d8e75e5775f0fac3f
      
https://github.com/qemu/qemu/commit/5b49a34c6800d0cb917f959d8e75e5775f0fac3f
  Author: Damien Hedde <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/arm/xilinx_zynq.c

  Log Message:
  -----------
  hw/arm/xilinx_zynq: connect uart clocks to slcr

Add the connection between the slcr's output clocks and the uarts inputs.

Also add the main board clock 'ps_clk', which is hard-coded to 33.33MHz
(the default frequency). This clock is used to feed the slcr's input
clock.

Signed-off-by: Damien Hedde <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9f2ff99c7f2392fe30e9e74d3e26a4c01820f53e
      
https://github.com/qemu/qemu/commit/9f2ff99c7f2392fe30e9e74d3e26a4c01820f53e
  Author: Damien Hedde <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M qdev-monitor.c

  Log Message:
  -----------
  qdev-monitor: print the device's clock with info qtree

This prints the clocks attached to a DeviceState when using
"info qtree" monitor command. For every clock, it displays the
direction, the name and if the clock is forwarded. For input clock,
it displays also the frequency.

This is based on the original work of Frederic Konrad.

Here follows a sample of `info qtree` output on xilinx_zynq machine
after linux boot with only one uart clocked:
> bus: main-system-bus
>  type System
>  [...]
>  dev: cadence_uart, id ""
>    gpio-out "sysbus-irq" 1
>    clock-in "refclk" freq_hz=0.000000e+00
>    chardev = ""
>    mmio 00000000e0001000/0000000000001000
>  dev: cadence_uart, id ""
>    gpio-out "sysbus-irq" 1
>    clock-in "refclk" freq_hz=1.375661e+07
>    chardev = "serial0"
>    mmio 00000000e0000000/0000000000001000
>  [...]
>  dev: xilinx,zynq_slcr, id ""
>    clock-out "uart1_ref_clk" freq_hz=0.000000e+00
>    clock-out "uart0_ref_clk" freq_hz=1.375661e+07
>    clock-in "ps_clk" freq_hz=3.333333e+07
>    mmio 00000000f8000000/0000000000001000

Signed-off-by: Damien Hedde <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 681b5bc32322fd0ff4338c550ec24612512d1a2e
      
https://github.com/qemu/qemu/commit/681b5bc32322fd0ff4338c550ec24612512d1a2e
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/arm/xlnx-versal.c

  Log Message:
  -----------
  hw/arm: versal: Setup the ADMA with 128bit bus-width

Setup the ADMA with 128bit bus-width. This matters when
FIXED BURST mode is used.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f1e7cb1388e46eac8285854af2abdfde41ffa226
      
https://github.com/qemu/qemu/commit/f1e7cb1388e46eac8285854af2abdfde41ffa226
  Author: Ramon Fried <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/net/cadence_gem.c

  Log Message:
  -----------
  Cadence: gem: fix wraparound in 64bit descriptors

Wraparound of TX descriptor cyclic buffer only updated
the low 32 bits of the descriptor.
Fix that by checking if we're working with 64bit descriptors.

Signed-off-by: Ramon Fried <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 59ab136a9e24f989cb7922d9cf7d1774fc497a78
      
https://github.com/qemu/qemu/commit/59ab136a9e24f989cb7922d9cf7d1774fc497a78
  Author: Ramon Fried <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/net/cadence_gem.c

  Log Message:
  -----------
  net: cadence_gem: clear RX control descriptor

The RX ring descriptors control field is used for setting
SOF and EOF (start of frame and end of frame).
The SOF and EOF weren't cleared from the previous descriptors,
causing inconsistencies in ring buffer.
Fix that by clearing the control field of every descriptors we're
processing.

Signed-off-by: Ramon Fried <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6b375d3546b009d1e63e07397ec9c6af256e15e9
      
https://github.com/qemu/qemu/commit/6b375d3546b009d1e63e07397ec9c6af256e15e9
  Author: Richard Henderson <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/neon_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Vectorize integer comparison vs zero

These instructions are often used in glibc's string routines.
They were the final uses of the 32-bit at a time neon helpers.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ef6a5c71c2f40e253712ad3d8826d5e84e325aeb
      
https://github.com/qemu/qemu/commit/ef6a5c71c2f40e253712ad3d8826d5e84e325aeb
  Author: Jerome Forissier <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: dt: move creation of /secure-chosen to create_fdt()

The /secure-chosen node is currently used only by create_uart(), but
this will change. Therefore move the creation of this node to
create_fdt().

Signed-off-by: Jerome Forissier <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 60592cfed2b685ef114a454d176ef539528cb0cf
      
https://github.com/qemu/qemu/commit/60592cfed2b685ef114a454d176ef539528cb0cf
  Author: Jerome Forissier <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: dt: add kaslr-seed property

Generate random seeds to be used by the non-secure and/or secure OSes
for ASLR. The seeds are 64-bit random values exported via the DT
properties /chosen/kaslr-seed [1] and /secure-chosen/kaslr-seed, the
latter being used by OP-TEE [2].

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e5bc0c37c97e1
[2] https://github.com/OP-TEE/optee_os/commit/ef262691fe0e

Signed-off-by: Jerome Forissier <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9fb005b02dbda7f47b789b7f19bf5f73622a4756
      
https://github.com/qemu/qemu/commit/9fb005b02dbda7f47b789b7f19bf5f73622a4756
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Restrict the Address Translate write operation to TCG accel

Under KVM these registers are written by the hardware.
Restrict the writefn handlers to TCG to avoid when building
without TCG:

      LINK    aarch64-softmmu/qemu-system-aarch64
    target/arm/helper.o: In function `do_ats_write':
    target/arm/helper.c:3524: undefined reference to `raise_exception'

Suggested-by: Richard Henderson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 37bcf244454f4efb82e2c0c64bbd7eabcc165a0c
      
https://github.com/qemu/qemu/commit/37bcf244454f4efb82e2c0c64bbd7eabcc165a0c
  Author: Thomas Huth <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M target/arm/cpu-qom.h
    M target/arm/cpu.c
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Make cpu_register() available for other files

Make cpu_register() (renamed to arm_cpu_register()) available
from internals.h so we can register CPUs also from other files
in the future.

Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Message-ID: <address@hidden>
[PMD: Only take cpu_register() from Thomas's patch]
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 51c510aa5876a681cd0059ed3bacaa17590dc2d5
      
https://github.com/qemu/qemu/commit/51c510aa5876a681cd0059ed3bacaa17590dc2d5
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm/cpu: Update coding style to make checkpatch.pl happy

We will move this code in the next commit. Clean it up
first to avoid checkpatch.pl errors.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 80972d3bb2dbc6a47bae84b694c14acba9c1de64
      
https://github.com/qemu/qemu/commit/80972d3bb2dbc6a47bae84b694c14acba9c1de64
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M device_tree.c
    M include/sysemu/device_tree.h

  Log Message:
  -----------
  device_tree: Allow name wildcards in qemu_fdt_node_path()

Allow name wildcards in qemu_fdt_node_path(). This is useful
to find all nodes with a given compatibility string.

Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 958bae18b26ea7183865c8876c04441edfed3760
      
https://github.com/qemu/qemu/commit/958bae18b26ea7183865c8876c04441edfed3760
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M device_tree.c
    M include/sysemu/device_tree.h

  Log Message:
  -----------
  device_tree: Constify compat in qemu_fdt_node_path()

Make compat in qemu_fdt_node_path() const char *.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4d1ac883a7635c4bd58991bc158eff0c81cb230c
      
https://github.com/qemu/qemu/commit/4d1ac883a7635c4bd58991bc158eff0c81cb230c
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/arm/xlnx-zcu102.c

  Log Message:
  -----------
  hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102

Move arm_boot_info into XlnxZCU102.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6f7b6947a6639fff15c6a0956adf0f5ec004b789
      
https://github.com/qemu/qemu/commit/6f7b6947a6639fff15c6a0956adf0f5ec004b789
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M hw/arm/xlnx-zcu102.c

  Log Message:
  -----------
  hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes

Disable unsupported FDT firmware nodes if a user passes us
a DTB with nodes enabled that the machine cannot support
due to lack of EL3 or EL2 support.

Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 126eeee6c7b516e0a348dd4d60e59dbfa4b4b513
      
https://github.com/qemu/qemu/commit/126eeee6c7b516e0a348dd4d60e59dbfa4b4b513
  Author: Peter Maydell <address@hidden>
  Date:   2020-04-30 (Thu, 30 Apr 2020)

  Changed paths:
    M MAINTAINERS
    M device_tree.c
    A docs/devel/clocks.rst
    M docs/devel/index.rst
    M hw/acpi/cpu.c
    M hw/arm/msf2-soc.c
    M hw/arm/virt.c
    M hw/arm/xilinx_zynq.c
    M hw/arm/xlnx-versal.c
    M hw/arm/xlnx-zcu102.c
    M hw/char/cadence_uart.c
    M hw/char/trace-events
    M hw/core/Makefile.objs
    A hw/core/clock-vmstate.c
    A hw/core/clock.c
    A hw/core/qdev-clock.c
    M hw/core/qdev.c
    M hw/core/trace-events
    M hw/dma/xlnx-zdma.c
    M hw/intc/arm_gicv3_kvm.c
    M hw/misc/zynq_slcr.c
    M hw/net/Makefile.objs
    M hw/net/cadence_gem.c
    A hw/net/msf2-emac.c
    M include/hw/arm/msf2-soc.h
    M include/hw/char/cadence_uart.h
    A include/hw/clock.h
    M include/hw/gpio/nrf51_gpio.h
    A include/hw/net/msf2-emac.h
    A include/hw/qdev-clock.h
    M include/hw/qdev-core.h
    M include/sysemu/device_tree.h
    M qdev-monitor.c
    M target/arm/cpu-qom.h
    M target/arm/cpu.c
    M target/arm/cpu64.c
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/neon_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h
    M target/arm/vec_helper.c
    M tests/Makefile.include
    M tests/acceptance/boot_linux_console.py

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20200430-1' into staging

target-arm queue:
 * xlnx-zdma: Fix endianness handling of descriptor loading
 * nrf51: Fix last GPIO CNF address
 * gicv3: Use gicr_typer in arm_gicv3_icc_reset
 * msf2: Add EMAC block to SmartFusion2 SoC
 * New clock modelling framework
 * hw/arm: versal: Setup the ADMA with 128bit bus-width
 * Cadence: gem: fix wraparound in 64bit descriptors
 * cadence_gem: clear RX control descriptor
 * target/arm: Vectorize integer comparison vs zero
 * hw/arm/virt: dt: add kaslr-seed property
 * hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes

# gpg: Signature made Thu 30 Apr 2020 15:43:54 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200430-1: (30 commits)
  hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes
  hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102
  device_tree: Constify compat in qemu_fdt_node_path()
  device_tree: Allow name wildcards in qemu_fdt_node_path()
  target/arm/cpu: Update coding style to make checkpatch.pl happy
  target/arm: Make cpu_register() available for other files
  target/arm: Restrict the Address Translate write operation to TCG accel
  hw/arm/virt: dt: add kaslr-seed property
  hw/arm/virt: dt: move creation of /secure-chosen to create_fdt()
  target/arm: Vectorize integer comparison vs zero
  net: cadence_gem: clear RX control descriptor
  Cadence: gem: fix wraparound in 64bit descriptors
  hw/arm: versal: Setup the ADMA with 128bit bus-width
  qdev-monitor: print the device's clock with info qtree
  hw/arm/xilinx_zynq: connect uart clocks to slcr
  hw/char/cadence_uart: add clock support
  hw/misc/zynq_slcr: add clock generation for uarts
  docs/clocks: add device's clock documentation
  qdev-clock: introduce an init array to ease the device construction
  qdev: add clock input&output support to devices.
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/16aaacb307ed...126eeee6c7b5