[Qemu-commits] [qemu/qemu] cb9fb6: ppc/spapr: Set the effective address provided flag...

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: cb9fb64d0789a3ec47eb0d7549026e353e98b8c1
      
https://github.com/qemu/qemu/commit/cb9fb64d0789a3ec47eb0d7549026e353e98b8c1
  Author: Mahesh Salgaonkar <address@hidden>
  Date:   2020-03-24 (Tue, 24 Mar 2020)

  Changed paths:
    M hw/ppc/spapr_events.c

  Log Message:
  -----------
  ppc/spapr: Set the effective address provided flag in mc error log.

Per PAPR, it is expected to set effective address provided flag in
sub_err_type member of mc extended error log (i.e
rtas_event_log_v6_mc.sub_err_type). This somehow got missed in original
fwnmi-mce patch series. The current code just updates the effective address
but does not set the flag to indicate that it is available. Hence guest
fails to extract effective address from mce rtas log. This patch fixes
that.

Without this patch guest MCE logs fails print DAR value:

[   11.933608] Disabling lock debugging due to kernel taint
[   11.933773] MCE: CPU0: machine check (Severe) Host TLB Multihit [Recovered]
[   11.933979] MCE: CPU0: NIP: [c000000000090b34] 
radix__flush_tlb_range_psize+0x194/0xf00
[   11.934223] MCE: CPU0: Initiator CPU
[   11.934341] MCE: CPU0: Unknown

After the change:

[   22.454149] Disabling lock debugging due to kernel taint
[   22.454316] MCE: CPU0: machine check (Severe) Host TLB Multihit DAR: 
deadbeefdeadbeef [Recovered]
[   22.454605] MCE: CPU0: NIP: [c0000000003e5804] kmem_cache_alloc+0x84/0x330
[   22.454820] MCE: CPU0: Initiator CPU
[   22.454944] MCE: CPU0: Unknown

Signed-off-by: Mahesh Salgaonkar <address@hidden>
Message-Id: <158451653844.22972.17999316676230071087.stgit@jupiter>
Reviewed-by: Nicholas Piggin <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f9e3e1a35e8fd63d61fae58bd98d24d7defa9316
      
https://github.com/qemu/qemu/commit/f9e3e1a35e8fd63d61fae58bd98d24d7defa9316
  Author: Nicholas Piggin <address@hidden>
  Date:   2020-03-24 (Tue, 24 Mar 2020)

  Changed paths:
    M target/ppc/mmu-hash64.c

  Log Message:
  -----------
  target/ppc: Fix slbia TLB invalidation gap

slbia must invalidate TLBs even if it does not remove a valid SLB
entry, because slbmte can overwrite valid entries without removing
their TLBs.

As the architecture says, slbia invalidates all lookaside information,
not conditionally based on if it removed valid entries.

It does not seem possible for POWER8 or earlier Linux kernels to hit
this bug because it never changes its kernel SLB translations, and it
should always have valid entries if any accesses are made to userspace
regions. However other operating systems which may modify SLB entry 0
or do more fancy things with segments might be affected.

When POWER9 slbia support is added in the next patch, this becomes a
real problem because some new slbia variants don't invalidate all
non-zero entries.

Signed-off-by: Nicholas Piggin <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0418bf78fe8e61e619782940e77ca2d18b8c2d35
      
https://github.com/qemu/qemu/commit/0418bf78fe8e61e619782940e77ca2d18b8c2d35
  Author: Nicholas Piggin <address@hidden>
  Date:   2020-03-24 (Tue, 24 Mar 2020)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/mmu-hash64.c
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Fix ISA v3.0 (POWER9) slbia implementation

The new ISA v3.0 slbia variants have not been implemented for TCG,
which can lead to crashing when a POWER9 machine boots Linux using
the hash MMU, for example ("disable_radix" kernel command line).

Add them.

Signed-off-by: Nicholas Piggin <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
[dwg: Fixed compile error for USER_ONLY builds]
Signed-off-by: David Gibson <address@hidden>


  Commit: feb39b62288cb780561ca83b84ca82dceb3cedb9
      
https://github.com/qemu/qemu/commit/feb39b62288cb780561ca83b84ca82dceb3cedb9
  Author: Vincent Fazio <address@hidden>
  Date:   2020-03-24 (Tue, 24 Mar 2020)

  Changed paths:
    M linux-user/ppc/signal.c

  Log Message:
  -----------
  target/ppc: don't byte swap ELFv2 signal handler

Previously, the signal handler would be byte swapped if the target and
host CPU used different endianness. This would cause a SIGSEGV when
attempting to translate the opcode pointed to by the swapped address.

 Thread 1 "qemu-ppc64" received signal SIGSEGV, Segmentation fault.
 0x00000000600a9257 in ldl_he_p (ptr=0x4c2c061000000000) at 
qemu/include/qemu/bswap.h:351
 351        __builtin_memcpy(&r, ptr, sizeof(r));

 #0  0x00000000600a9257 in ldl_he_p (ptr=0x4c2c061000000000) at 
qemu/include/qemu/bswap.h:351
 #1  0x00000000600a92fe in ldl_be_p (ptr=0x4c2c061000000000) at 
qemu/include/qemu/bswap.h:449
 #2  0x00000000600c0790 in translator_ldl_swap at 
qemu/include/exec/translator.h:201
 #3  0x000000006011c1ab in ppc_tr_translate_insn at 
qemu/target/ppc/translate.c:7856
 #4  0x000000006005ae70 in translator_loop at qemu/accel/tcg/translator.c:102

The signal handler will be byte swapped as a result of the __get_user()
call in sigaction() if it is necessary, no additional swap is required.

Signed-off-by: Vincent Fazio <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: ce05fa0fcc9e23d16b2ff079cb3cb6aceaccbc28
      
https://github.com/qemu/qemu/commit/ce05fa0fcc9e23d16b2ff079cb3cb6aceaccbc28
  Author: Greg Kurz <address@hidden>
  Date:   2020-03-24 (Tue, 24 Mar 2020)

  Changed paths:
    M hw/ppc/spapr_hcall.c

  Log Message:
  -----------
  spapr: Fix memory leak in h_client_architecture_support()

This is the only error path that needs to free the previously allocated
ov1.

Reported-by: Coverity (CID 1421924)
Fixes: cbd0d7f36322 "spapr: Fail CAS if option vector table cannot be parsed"
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 235352ee6e73d7716d20e706d484fd45c232ec09
      
https://github.com/qemu/qemu/commit/235352ee6e73d7716d20e706d484fd45c232ec09
  Author: Peter Maydell <address@hidden>
  Date:   2020-03-24 (Tue, 24 Mar 2020)

  Changed paths:
    M target/ppc/timebase_helper.c

  Log Message:
  -----------
  hw/ppc: Take QEMU lock when calling ppc_dcr_read/write()

The ppc_dcr_read() and ppc_dcr_write() functions call into callbacks
in device code, so we need to hold the QEMU iothread lock while
calling them.  This is the case already for the callsites in
kvmppc_handle_dcr_read/write(), but we must also take the lock when
calling the helpers from TCG.

This fixes a bug where attempting to initialise the PPC405EP
SDRAM will cause an assertion when sdram_map_bcr() attempts
to remap memory regions.

Reported-by: Amit Lazar <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 1583794b9b36911df116cc726750dadbeeac506a
      
https://github.com/qemu/qemu/commit/1583794b9b36911df116cc726750dadbeeac506a
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2020-03-24 (Tue, 24 Mar 2020)

  Changed paths:
    M hw/ppc/ppc405_boards.c

  Log Message:
  -----------
  ppc/ppc405_boards: Remove unnecessary NULL check

This code is inside the "if (dinfo)" condition, so testing
again here whether it is NULL is unnecessary.

Fixes: dd59bcae7 (Don't size flash memory to match backing image)
Reported-by: Coverity (CID 1421917)
Suggested-by: Peter Maydell <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 09a98dd988c715157c0b80af16fa5baa80101eed
      
https://github.com/qemu/qemu/commit/09a98dd988c715157c0b80af16fa5baa80101eed
  Author: Peter Maydell <address@hidden>
  Date:   2020-03-24 (Tue, 24 Mar 2020)

  Changed paths:
    M hw/ppc/ppc405_boards.c
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_hcall.c
    M linux-user/ppc/signal.c
    M target/ppc/helper.h
    M target/ppc/mmu-hash64.c
    M target/ppc/timebase_helper.c
    M target/ppc/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20200324' into 
staging

ppc patch queue for 2020-03-24

Here's a final pull request before the qemu-5.0 hard freeze.

We have an implementation of the POWER9 forms of the slbia
instruction, a small cleanup and a handful of assorted fixes.

# gpg: Signature made Tue 24 Mar 2020 05:12:30 GMT
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>" [full]
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>" [full]
# gpg:                 aka "David Gibson (kernel.org) <address@hidden>" 
[unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-5.0-20200324:
  ppc/ppc405_boards: Remove unnecessary NULL check
  hw/ppc: Take QEMU lock when calling ppc_dcr_read/write()
  spapr: Fix memory leak in h_client_architecture_support()
  target/ppc: don't byte swap ELFv2 signal handler
  target/ppc: Fix ISA v3.0 (POWER9) slbia implementation
  target/ppc: Fix slbia TLB invalidation gap
  ppc/spapr: Set the effective address provided flag in mc error log.

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/f1e748d27996...09a98dd988c7