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[Qemu-commits] [qemu/qemu] 35dde5: ppc/pnv: Add a PNOR model
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 35dde5: ppc/pnv: Add a PNOR model |
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Date: |
Tue, 17 Dec 2019 06:45:14 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 35dde5766211cac0e608b29b3f71922f116b5932
https://github.com/qemu/qemu/commit/35dde5766211cac0e608b29b3f71922f116b5932
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/Makefile.objs
M hw/ppc/pnv.c
A hw/ppc/pnv_pnor.c
M include/hw/ppc/pnv.h
A include/hw/ppc/pnv_pnor.h
Log Message:
-----------
ppc/pnv: Add a PNOR model
On a POWERPC PowerNV system, the host firmware is stored in a PNOR
flash chip which contents is mapped on the LPC bus. This model adds a
simple dummy device to map the contents of a block device in the host
address space.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ccb099b3bf6c8682153fa8d864646f2fadded40a
https://github.com/qemu/qemu/commit/ccb099b3bf6c8682153fa8d864646f2fadded40a
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Add a "/qemu" device tree node
It helps skiboot identifying that is running on a QEMU platform. The
compatible string will define the POWERPC processor version.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 719ed8461fdca7ffe67778014be110c8e6dd4fb3
https://github.com/qemu/qemu/commit/719ed8461fdca7ffe67778014be110c8e6dd4fb3
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Drop "chip" link from POWER9 PSI object
It has no apparent user.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 411c2a619e713bbfa175e72ed6d754a673e299fc
https://github.com/qemu/qemu/commit/411c2a619e713bbfa175e72ed6d754a673e299fc
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
xive: Link "cpu" property to XiveTCTX::cs pointer
The TCTX object has both a pointer and a "cpu" property pointing to the
vCPU object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 82ea3a1b291527ef67315f00e50cbbc105b7d739
https://github.com/qemu/qemu/commit/82ea3a1b291527ef67315f00e50cbbc105b7d739
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/pnv_xive.c
M hw/intc/spapr_xive.c
M hw/intc/xive.c
M hw/ppc/pnv_psi.c
Log Message:
-----------
xive: Link "xive" property to XiveSource::xive pointer
The source object has both a pointer and a "xive" property pointing to the
notifier object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
The property isn't optional : not being able to set the link is a bug
and QEMU should rather abort than exit in this case.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 0ab2316e9e605af500fcefc60e39c8dc62fbd161
https://github.com/qemu/qemu/commit/0ab2316e9e605af500fcefc60e39c8dc62fbd161
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/pnv_xive.c
M hw/intc/spapr_xive.c
M hw/intc/xive.c
Log Message:
-----------
xive: Link "xive" property to XiveEndSource::xrtr pointer
The END source object has both a pointer and a "xive" property pointing to
the router object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
The property isn't optional : not being able to set the link is a bug
and QEMU should rather abort than exit in this case.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b63f389366fbc586ce82f95ad808a51bc9f95c71
https://github.com/qemu/qemu/commit/b63f389366fbc586ce82f95ad808a51bc9f95c71
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_lpc.c
Log Message:
-----------
ppc/pnv: Link "psi" property to PnvLpc::psi pointer
The LPC object has both a pointer and a "psi" property pointing to the
PSI object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ee3d27138da0cc44ba29258dc66c85ac9c4a6bad
https://github.com/qemu/qemu/commit/ee3d27138da0cc44ba29258dc66c85ac9c4a6bad
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_occ.c
Log Message:
-----------
ppc/pnv: Link "psi" property to PnvOCC::psi pointer
The OCC object has both a pointer and a "psi" property pointing to the
PSI object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f2582acf993f2f62bba5c8d74726a199abe3a491
https://github.com/qemu/qemu/commit/f2582acf993f2f62bba5c8d74726a199abe3a491
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_homer.c
Log Message:
-----------
ppc/pnv: Link "chip" property to PnvHomer::chip pointer
The homer object has both a pointer and a "chip" property pointing to the
chip object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 158e17a65e1ad0f2bd1e300c2f30f9481901a485
https://github.com/qemu/qemu/commit/158e17a65e1ad0f2bd1e300c2f30f9481901a485
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
Log Message:
-----------
ppc/pnv: Link "chip" property to PnvCore::chip pointer
The core object has both a pointer and a "chip" property pointing to the
chip object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 7ae54cc3a00d28cfb0bc4f377faf157b2e55b25c
https://github.com/qemu/qemu/commit/7ae54cc3a00d28cfb0bc4f377faf157b2e55b25c
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/pnv_xive.c
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Link "chip" property to PnvXive::chip pointer
The XIVE object has both a pointer and a "chip" property pointing to the
chip object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b015a9809427c87940447e5b76a5b73a0bf27d7c
https://github.com/qemu/qemu/commit/b015a9809427c87940447e5b76a5b73a0bf27d7c
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/xics.c
M hw/ppc/pnv_psi.c
M hw/ppc/spapr_irq.c
Log Message:
-----------
xics: Link ICS_PROP_XICS property to ICSState::xics pointer
The ICS object has both a pointer and an ICS_PROP_XICS property pointing
to the XICS fabric. Confusing bugs could arise if these ever go out of
sync.
Change the property definition so that it explicitely sets the pointer.
The property isn't optional : not being able to set the link is a bug
and QEMU should rather abort than exit in this case.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b4a378a7c5de55333afa4d71b14c18c85b3cba6b
https://github.com/qemu/qemu/commit/b4a378a7c5de55333afa4d71b14c18c85b3cba6b
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/xics.c
Log Message:
-----------
xics: Link ICP_PROP_XICS property to ICPState::xics pointer
The ICP object has both a pointer and an ICP_PROP_XICS property pointing
to the XICS fabric. Confusing bugs could arise if these ever go out of
sync.
Change the property definition so that it explicitly sets the pointer.
The property isn't optional : not being able to set the link is a bug
and QEMU should rather abort than exit in this case.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e388d66b407366e09228fa60b783cea1ac828066
https://github.com/qemu/qemu/commit/e388d66b407366e09228fa60b783cea1ac828066
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/xics.c
Log Message:
-----------
xics: Link ICP_PROP_CPU property to ICPState::cs pointer
The ICP object has both a pointer and an ICP_PROP_CPU property pointing
to the cpu. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitly sets the pointer.
The property isn't optional : not being able to set the link is a bug
and QEMU should rather abort than exit in this case.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 818a6d30e0011e7a9cf8b1d4a1d6f3255778e1d7
https://github.com/qemu/qemu/commit/818a6d30e0011e7a9cf8b1d4a1d6f3255778e1d7
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/spapr_irq.c
Log Message:
-----------
spapr: Abort if XICS interrupt controller cannot be initialized
Failing to set any of the ICS property should really never happen:
- object_property_add_child() always succeed unless the child object
already has a parent, which isn't the case here obviously since the
ICS has just been created with object_new()
- the ICS has an "nr-irqs" property than can be set as long as the ICS
isn't realized
In both cases, an error indicates there is a bug in QEMU. Propagating the
error, ie. exiting QEMU since spapr_irq_init() is called with &error_fatal
doesn't make much sense. Abort instead. This is consistent with what is
done with XIVE : both qdev_create() and qdev_prop_set_uint32() abort QEMU
on error.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 95bd61c4dfc4c08d4248071f2f70d9c2afacc0d1
https://github.com/qemu/qemu/commit/95bd61c4dfc4c08d4248071f2f70d9c2afacc0d1
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv_lpc.c
Log Message:
-----------
ppc/pnv: Add a LPC "ranges" property
And fix a typo in the MEM address space definition.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 516883c2f15bdd844543be218155898d06953c90
https://github.com/qemu/qemu/commit/516883c2f15bdd844543be218155898d06953c90
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/xive.c
M include/hw/ppc/xive_regs.h
Log Message:
-----------
ppc/xive: Record the IPB in the associated NVT
When an interrupt can not be presented to a vCPU, because it is not
running on any of the HW treads, the XIVE presenter updates the
Interrupt Pending Buffer register of the associated XIVE NVT
structure. This is only done if backlog is activated in the END but
this is generally the case.
The current code assumes that the fields of the NVT structure is
architected with the same layout of the thread interrupt context
registers. Fix this assumption and define an offset for the IPB
register backup value in the NVT.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e6488eeba89e559f284a40aeafde347d7d0a86a8
https://github.com/qemu/qemu/commit/e6488eeba89e559f284a40aeafde347d7d0a86a8
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M include/hw/ppc/xive.h
M include/hw/ppc/xive_regs.h
Log Message:
-----------
ppc/xive: Introduce helpers for the NVT id
Each vCPU in the system is identified with an NVT identifier which is
pushed in the OS CAM line (QW1W2) of the HW thread interrupt context
register when the vCPU is dispatched on a HW thread. This identifier
is used by the presenter subengine to find a matching target to notify
of an event. It is also used to fetch the associate NVT structure
which may contain pending interrupts that need a resend.
Add a couple of helpers for the NVT ids. The NVT space is 19 bits
wide, giving a maximum of 512K per chip.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 7aa22e18092e8eef2bcc77f247576fa44980c7cb
https://github.com/qemu/qemu/commit/7aa22e18092e8eef2bcc77f247576fa44980c7cb
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/pnv_xive.c
Log Message:
-----------
ppc/pnv: Remove pnv_xive_vst_size() routine
pnv_xive_vst_size() tries to compute the size of a VSD table from the
information given by FW. The number of entries of the table are
deduced from the result and the MMIO regions of the ESBs and the END
ESBs are then resized accordingly with the computed value. This
reduces the number of elements that can be addressed by the ESB pages.
The maximum number of elements of a direct table can contain is simply:
Table size / sizeof(XIVE structure)
An indirect table is a one page array of VSDs pointing to subpages
containing XIVE virtual structures and the maximum number of elements
an indirect table can contain :
(PAGE_SIZE / sizeof(vsd)) * (PAGE_SIZE / sizeof(XIVE structure))
which gives us 16M for XiveENDs, 8M for XiveNVTs. That's more than the
associated VC and PC BARS can address.
The result returned by pnv_xive_vst_size() for indirect tables is
incorrect and can not be used to reduce the size of the MMIO region of
a XIVE resource using an indirect table, such as ENDs in skiboot.
Remove pnv_xive_vst_size() and use a simpler form for direct tables
only. Keep the resizing of the MMIO region for direct tables only as
this is still useful for the ESB MMIO window.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 58246041d372f5b1cd7ec5242b44dbd5c3a556c4
https://github.com/qemu/qemu/commit/58246041d372f5b1cd7ec5242b44dbd5c3a556c4
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/spapr_xive_kvm.c
Log Message:
-----------
xive/kvm: Trigger interrupts from userspace
When using the XIVE KVM device, the trigger page is directly accessible
in QEMU. Unlike with XICS, no need to ask KVM to fire the interrupt. A
simple store on the trigger page does the job.
Just call xive_esb_trigger().
This may improve performance of emulated devices that go through
qemu_set_irq(), eg. virtio devices created with ioeventfd=off or
configured by the guest to use LSI interrupts, which aren't really
recommended setups.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: cd55b1272e3fa341b3f7c32b6186a2d0f71a45c8
https://github.com/qemu/qemu/commit/cd55b1272e3fa341b3f7c32b6186a2d0f71a45c8
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/pnv_xive.c
Log Message:
-----------
ppc/pnv: Quiesce some XIVE errors
When dumping the END and NVT tables, the error logging is too noisy.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 7065d0670a7a542633d33d639623f60663384ffd
https://github.com/qemu/qemu/commit/7065d0670a7a542633d33d639623f60663384ffd
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: Introduce OS CAM line helpers
The OS CAM line has a special encoding exploited by the HW. Provide
helper routines to hide the details to the TIMA command handlers. This
also clarifies the endianness of different variables : 'qw1w2' is
big-endian and 'cam' is native.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1c27b252e7b5d6a54f5083781b1d2a0e425b04df
https://github.com/qemu/qemu/commit/1c27b252e7b5d6a54f5083781b1d2a0e425b04df
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: Check V bit in TM_PULL_POOL_CTX
A context should be 'valid' when pulled from the thread interrupt
context registers.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ed8da05cdb18a32a8a41165d5b7b367bc05fdab0
https://github.com/qemu/qemu/commit/ed8da05cdb18a32a8a41165d5b7b367bc05fdab0
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ipmi/ipmi_bmc_sim.c
M include/hw/ipmi/ipmi.h
Log Message:
-----------
ipmi: Add support to customize OEM functions
The routine ipmi_register_oem_netfn() lets external modules register
command handlers for OEM functions. Required for the PowerNV machine.
Cc: Corey Minyard <address@hidden>
Reviewed-by: Corey Minyard <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Acked-by: Corey Minyard <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ca661fae81d3b36b72c316a63165d9318dbd2439
https://github.com/qemu/qemu/commit/ca661fae81d3b36b72c316a63165d9318dbd2439
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_bmc.c
M hw/ppc/pnv_lpc.c
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_pnor.h
Log Message:
-----------
ppc/pnv: Add HIOMAP commands
This activates HIOMAP support on the QEMU PowerNV machine. The PnvPnor
model is used to access the flash contents. The model simply maps the
contents at a fix offset and enables or disables the mapping.
HIOMAP Protocol description :
https://github.com/openbmc/hiomapd/blob/master/Documentation/protocol.md
Reviewed-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e2392d4395ddc18a1e991f30f7dbea8cf02ec8e6
https://github.com/qemu/qemu/commit/e2392d4395ddc18a1e991f30f7dbea8cf02ec8e6
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_bmc.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Create BMC devices at machine init
The BMC of the OpenPOWER systems monitors the machine state using
sensors, controls the power and controls the access to the PNOR flash
device containing the firmware image required to boot the host.
QEMU models the power cycle process, access to the sensors and access
to the PNOR device. But, for these features to be available, the QEMU
PowerNV machine needs two extras devices on the command line, an IPMI
BT device for communication and a BMC backend device:
-device ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10
The BMC properties are then defined accordingly in the device tree and
OPAL self adapts. If a BMC device and an IPMI BT device are not
available, OPAL does not try to communicate with the BMC in any
manner. This is not how real systems behave.
To be closer to the default behavior, create an IPMI BMC simulator
device and an IPMI BT device at machine initialization time. We loose
the ability to define an external BMC device but there are benefits:
- a better match with real systems,
- a better test coverage of the OPAL code,
- system powerdown and reset commands that work,
- a QEMU device tree compliant with the specifications (*).
(*) Still needs a MBOX device.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 13bee8521c2e1d4908b1e003ff50fdec3702ad13
https://github.com/qemu/qemu/commit/13bee8521c2e1d4908b1e003ff50fdec3702ad13
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/xive.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/xive: Introduce a XivePresenter interface
When the XIVE IVRE sub-engine (XiveRouter) looks for a Notification
Virtual Target (NVT) to notify, it broadcasts a message on the
PowerBUS to find an XIVE IVPE sub-engine (Presenter) with the NVT
dispatched on one of its HW threads, and then forwards the
notification if any response was received.
The current XIVE presenter model is sufficient for the pseries machine
because it has a single interrupt controller device, but the PowerNV
machine can have multiple chips each having its own interrupt
controller. In this case, the XIVE presenter model is too simple and
the CAM line matching should scan all chips of the system.
To start fixing this issue, we first extend the XIVE Router model with
a new XivePresenter QOM interface representing the XIVE IVPE
sub-engine. This interface exposes a 'match_nvt' handler which the
sPAPR and PowerNV XIVE Router models will need to implement to perform
the CAM line matching.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f87dae18d8675f8fef7b34e713d3951fb594d5be
https://github.com/qemu/qemu/commit/f87dae18d8675f8fef7b34e713d3951fb594d5be
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/pnv_xive.c
M hw/intc/spapr_xive.c
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: Implement the XivePresenter interface
Each XIVE Router model, sPAPR and PowerNV, now implements the 'match_nvt'
handler of the XivePresenter QOM interface. This is simply moving code
and taking into account the new API.
To be noted that the xive_router_get_tctx() helper is not used anymore
when doing CAM matching and will be removed later on after other changes.
The XIVE presenter model is still too simple for the PowerNV machine
and the CAM matching algo is not correct on multichip system. Subsequent
patches will introduce more changes to scan all chips of the system.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 4fa28f23906dc268c4c3be3236f15a4de1093c18
https://github.com/qemu/qemu/commit/4fa28f23906dc268c4c3be3236f15a4de1093c18
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Instantiate cores separately
Allocating a big void * array to store multiple objects isn't a
recommended practice for various reasons:
- no compile time type checking
- potential dangling pointers if a reference on an individual is
taken and the array is freed later on
- duplicate boiler plate everywhere the array is browsed through
Allocate an array of pointers and populate it instead.
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: feecc6a0435d46da45b2d383693fe1292043606c
https://github.com/qemu/qemu/commit/feecc6a0435d46da45b2d383693fe1292043606c
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/pnv_xive.c
Log Message:
-----------
ppc/pnv: Loop on the threads of the chip to find a matching NVT
CPU_FOREACH() loops on all the CPUs of the machine which is incorrect.
Each XIVE Presenter should scan only the HW threads of the chip it
belongs to.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 4a89e20458ef6ef0979d9a05e41b421fe28a90a8
https://github.com/qemu/qemu/commit/4a89e20458ef6ef0979d9a05e41b421fe28a90a8
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/ppc.c
M include/hw/ppc/ppc.h
Log Message:
-----------
ppc: Introduce a ppc_cpu_pir() helper
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5014c60261cf38b7c210831548c042982218a999
https://github.com/qemu/qemu/commit/5014c60261cf38b7c210831548c042982218a999
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/pnv_xive.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper
and use this helper to exclude CPUs which are not enabled in the XIVE
controller.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 119eaa9d11cb5245fae0a2cbe4f18dda55744dfb
https://github.com/qemu/qemu/commit/119eaa9d11cb5245fae0a2cbe4f18dda55744dfb
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/pnv_xive.c
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Fix TIMA indirect access
When the TIMA of a CPU needs to be accessed from the indirect page,
the thread id of the target CPU is first stored in the PC_TCTXT_INDIR0
register. This thread id is relative to the chip and not to the system.
Introduce a helper routine to look for a CPU of a given PIR and fix
pnv_xive_get_indirect_tctx() to scan only the threads of the local
chip and not the whole machine.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d3eb47a2a18f850c2ebd20e50d164251ad321128
https://github.com/qemu/qemu/commit/d3eb47a2a18f850c2ebd20e50d164251ad321128
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/xive.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/xive: Introduce a XiveFabric interface
The XiveFabric QOM interface acts as the PowerBUS interface between
the interrupt controller and the system and should be implemented by
the QEMU machine. On HW, the XIVE sub-engine is responsible for the
communication with the other chip is the Common Queue (CQ) bridge
unit.
This interface offers a 'match_nvt' handler to perform the CAM line
matching when looking for a XIVE Presenter with a dispatched NVT.
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c722579e8c55a66694146c24eb507f79c71ac881
https://github.com/qemu/qemu/commit/c722579e8c55a66694146c24eb507f79c71ac881
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Implement the XiveFabric interface
The CAM line matching on the PowerNV machine now scans all chips of
the system and all CPUs of a chip to find a dispatched NVT in the
thread contexts.
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 932de7aef82b234fd30e287766d0e0e34b095f78
https://github.com/qemu/qemu/commit/932de7aef82b234fd30e287766d0e0e34b095f78
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
ppc/spapr: Implement the XiveFabric interface
The CAM line matching sequence in the pseries machine does not change
much apart from the use of the new QOM interfaces. There is an extra
indirection because of the sPAPR IRQ backend of the machine. Only the
XIVE backend implements the new 'match_nvt' handler.
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5662f291677bc30fa006eccd61b1828a022261e0
https://github.com/qemu/qemu/commit/5662f291677bc30fa006eccd61b1828a022261e0
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: Use the XiveFabric and XivePresenter interfaces
Now that the machines have handlers implementing the XiveFabric and
XivePresenter interfaces, remove xive_presenter_match() and make use
of the 'match_nvt' handler of the machine.
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 4fb42350dc20d0974111451bd2d7383739822d09
https://github.com/qemu/qemu/commit/4fb42350dc20d0974111451bd2d7383739822d09
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/pnv_xive.c
M hw/intc/xive.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/xive: Extend the TIMA operation with a XivePresenter parameter
The TIMA operations are performed on behalf of the XIVE IVPE sub-engine
(Presenter) on the thread interrupt context registers. The current
operations supported by the model are simple and do not require access
to the controller but more complex operations will need access to the
controller NVT table and to its configuration.
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2a886794f1969020845d0085a41a884e01b357df
https://github.com/qemu/qemu/commit/2a886794f1969020845d0085a41a884e01b357df
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M include/standard-headers/linux/ethtool.h
M include/standard-headers/linux/virtio_ring.h
M linux-headers/asm-arm/kvm.h
M linux-headers/asm-arm64/kvm.h
M linux-headers/asm-mips/unistd_n32.h
M linux-headers/asm-mips/unistd_n64.h
M linux-headers/asm-mips/unistd_o32.h
M linux-headers/asm-powerpc/kvm.h
M linux-headers/linux/kvm.h
M linux-headers/linux/psp-sev.h
Log Message:
-----------
linux-headers: Update
Update to mainline commit be2eca94d144 ("Merge tag 'for-linus-5.5-1'`
of git://github.com/cminyard/linux-ipmi")
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 4ffb7496881ec361deaf1f51c41a933bde3cbf7b
https://github.com/qemu/qemu/commit/4ffb7496881ec361deaf1f51c41a933bde3cbf7b
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/intc/spapr_xive_kvm.c
M hw/intc/xics_kvm.c
M hw/intc/xics_spapr.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_irq.h
M include/hw/ppc/spapr_xive.h
M include/hw/ppc/xics_spapr.h
Log Message:
-----------
spapr: Pass the maximum number of vCPUs to the KVM interrupt controller
The XIVE and XICS-on-XIVE KVM devices on POWER9 hosts can greatly reduce
their consumption of some scarce HW resources, namely Virtual Presenter
identifiers, if they know the maximum number of vCPUs that may run in the
VM.
Prepare ground for this by passing the value down to xics_kvm_connect()
and kvmppc_xive_connect(). This is purely mechanical, no functional
change.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 894ea3ecd38f4d09353cea19bb20002892d2b8b3
https://github.com/qemu/qemu/commit/894ea3ecd38f4d09353cea19bb20002892d2b8b3
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/xics_kvm.c
Log Message:
-----------
spapr/xics: Configure number of servers in KVM
The XICS-on-XIVE KVM devices now has an attribute to configure the number
of interrupt servers. This allows to greatly optimize the usage of the VP
space in the XIVE HW, and thus to start a lot more VMs.
Only set this attribute if available in order to support older POWER9 KVM
and pre-POWER9 XICS KVM devices.
The XICS-on-XIVE KVM device now reports the exhaustion of VPs upon the
connection of the first VCPU. Check that in order to have a chance to
provide a hint to the user.
`
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 74f23d433268a5b8020fc9d037d4512a55fe4d31
https://github.com/qemu/qemu/commit/74f23d433268a5b8020fc9d037d4512a55fe4d31
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/spapr_xive_kvm.c
Log Message:
-----------
spapr/xive: Configure number of servers in KVM
The XIVE KVM devices now has an attribute to configure the number of
interrupt servers. This allows to greatly optimize the usage of the VP
space in the XIVE HW, and thus to start a lot more VMs.
Only set this attribute if available in order to support older POWER9
KVM.
The XIVE KVM device now reports the exhaustion of VPs upon the
connection of the first VCPU. Check that in order to have a chance
to provide a hint to the user.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5373c61d6a7ec29c2b1126cb908fd08e23b4247b
https://github.com/qemu/qemu/commit/5373c61d6a7ec29c2b1126cb908fd08e23b4247b
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/pnv_xive.c
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Clarify how the TIMA is accessed on a multichip system
The TIMA region gives access to the thread interrupt context registers
of a CPU. It is mapped at the same address on all chips and can be
accessed by any CPU of the system. To identify the chip from which the
access is being done, the PowerBUS uses a 'chip' field in the
load/store messages. QEMU does not model these messages, instead, we
extract the chip id from the CPU PIR and do a lookup at the machine
level to fetch the targeted interrupt controller.
Introduce pnv_get_chip() and pnv_xive_tm_get_xive() helpers to clarify
this process in pnv_xive_get_tctx(). The latter will be removed in the
subsequent patches but the same principle will be kept.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d024a2c1114fadd9b0692be4e594a9b8b31197af
https://github.com/qemu/qemu/commit/d024a2c1114fadd9b0692be4e594a9b8b31197af
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/pnv_xive.c
M hw/intc/spapr_xive.c
M hw/intc/xive.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/xive: Move the TIMA operations to the controller model
On the P9 Processor, the thread interrupt context registers of a CPU
can be accessed "directly" when by load/store from the CPU or
"indirectly" by the IC through an indirect TIMA page. This requires to
configure first the PC_TCTXT_INDIRx registers.
Today, we rely on the get_tctx() handler to deduce from the CPU PIR
the chip from which the TIMA access is being done. By handling the
TIMA memory ops under the interrupt controller model of each machine,
we can uniformize the TIMA direct and indirect ops under PowerNV. We
can also check that the CPUs have been enabled in the XIVE controller.
This prepares ground for the future versions of XIVE.
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 8b3aaaa1a9c2182ed9e3c406c90bb4257b43e753
https://github.com/qemu/qemu/commit/8b3aaaa1a9c2182ed9e3c406c90bb4257b43e753
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/pnv_xive.c
M hw/intc/spapr_xive.c
M hw/intc/xive.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/xive: Remove the get_tctx() XiveRouter handler
It is now unused.
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a5b841f18c1ffdf306f48ff6baccf5193d368c0b
https://github.com/qemu/qemu/commit/a5b841f18c1ffdf306f48ff6baccf5193d368c0b
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/xive.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/xive: Introduce a xive_tctx_ipb_update() helper
We will use it to resend missed interrupts when a vCPU context is
pushed on a HW thread.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d1f2a574b9f686a1ddc634c2c01381fdc04eb37c
https://github.com/qemu/qemu/commit/d1f2a574b9f686a1ddc634c2c01381fdc04eb37c
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: Synthesize interrupt from the saved IPB in the NVT
When a vCPU is dispatched on a HW thread, its context is pushed in the
thread registers and it is activated by setting the VO bit in the CAM
line word2. The HW grabs the associated NVT, pulls the IPB bits and
merges them with the IPB of the new context. If interrupts were missed
while the vCPU was not dispatched, these are synthesized in this
sequence.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: dc2526e45a0ffebc88d7ed007d906f669827f834
https://github.com/qemu/qemu/commit/dc2526e45a0ffebc88d7ed007d906f669827f834
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/pnv_xive.c
M include/hw/ppc/pnv_xive.h
Log Message:
-----------
ppc/pnv: Introduce a pnv_xive_block_id() helper
When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID field
overrides the hardwired chip ID in the Powerbus operations and for CAM
compares. This is typically used in the one block-per-chip configuration
to associate a unique block id number to each IC of the system.
Simplify the model with a pnv_xive_block_id() helper and remove
'tctx_chipid' which becomes useless.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f22f56dd483b27f8c4463dbb310029dd9161bb04
https://github.com/qemu/qemu/commit/f22f56dd483b27f8c4463dbb310029dd9161bb04
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/pnv_xive.c
M hw/intc/spapr_xive.c
M hw/intc/xive.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/pnv: Extend XiveRouter with a get_block_id() handler
When doing CAM line compares, fetch the block id from the interrupt
controller which can have set the PC_TCTXT_CHIPID field.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d302e0008034dd79c36ab311768689da395cb26f
https://github.com/qemu/qemu/commit/d302e0008034dd79c36ab311768689da395cb26f
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/pnv_xive.c
M include/hw/ppc/xive_regs.h
Log Message:
-----------
ppc/pnv: Dump the XIVE NVT table
This is useful to dump the saved contexts of the vCPUs : configuration
of the base END index of the vCPU and the Interrupt Pending Buffer
register, which is updated when an interrupt can not be presented.
When dumping the NVT table, we skip empty indirect pages which are not
necessarily allocated.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: cdcca22aabafc0496894ce05c80097684832c7d9
https://github.com/qemu/qemu/commit/cdcca22aabafc0496894ce05c80097684832c7d9
Author: Vladimir Sementsov-Ogievskiy <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/spapr.c
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
Log Message:
-----------
ppc: well form kvmppc_hint_smt_possible error hint helper
Make kvmppc_hint_smt_possible hint append helper well formed:
rename errp to errp_in, as it is IN-parameter here (which is unusual
for errp), rename function to be kvmppc_error_append_*_hint.
Signed-off-by: Vladimir Sementsov-Ogievskiy <address@hidden>
Reviewed-by: Marc-André Lureau <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 8deb8019d696c75e6ecaee7545026b62aba2f1bb
https://github.com/qemu/qemu/commit/8deb8019d696c75e6ecaee7545026b62aba2f1bb
Author: David Gibson <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/spapr_hcall.c
Log Message:
-----------
spapr: Don't trigger a CAS reboot for XICS/XIVE mode changeover
PAPR allows the interrupt controller used on a POWER9 machine (XICS or
XIVE) to be selected by the guest operating system, by using the
ibm,client-architecture-support (CAS) feature negotiation call.
Currently, if the guest selects an interrupt controller different from the
one selected at initial boot, this causes the system to be reset with the
new model and the boot starts again. This means we run through the SLOF
boot process twice, as well as any other bootloader (e.g. grub) in use
before the OS calls CAS. This can be confusing and/or inconvenient for
users.
Thanks to two fairly recent changes, we no longer need this reboot. 1) we
now completely regenerate the device tree when CAS is called (meaning we
don't need special case updates for all the device tree changes caused by
the interrupt controller mode change), 2) we now have explicit code paths
to activate and deactivate the different interrupt controllers, rather than
just implicitly calling those at machine reset time.
We can therefore eliminate the reboot for changing irq mode, simply by
putting a call to spapr_irq_update_active_intc() before we call
spapr_h_cas_compose_response() (which gives the updated device tree to
the guest firmware and OS).
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cedric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: 97b32a6afa78ae68fb16344b9a144b6f433f42a2
https://github.com/qemu/qemu/commit/97b32a6afa78ae68fb16344b9a144b6f433f42a2
Author: David Gibson <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: Improve handling of fdt buffer size
Previously, spapr_build_fdt() constructed the device tree in a fixed
buffer of size FDT_MAX_SIZE. This is a bit inflexible, but more
importantly it's awkward for the case where we use it during CAS. In
that case the guest firmware supplies a buffer and we have to
awkwardly check that what we generated fits into it afterwards, after
doing a lot of size checks during spapr_build_fdt().
Simplify this by having spapr_build_fdt() take a 'space' parameter.
For the CAS case, we pass in the buffer size provided by SLOF, for the
machine init case, we continue to pass FDT_MAX_SIZE.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cedric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: 0c21e073541cc093b4cb8744640e24f130e6f8ba
https://github.com/qemu/qemu/commit/0c21e073541cc093b4cb8744640e24f130e6f8ba
Author: David Gibson <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr: Fold h_cas_compose_response() into h_client_architecture_support()
spapr_h_cas_compose_response() handles the last piece of the PAPR feature
negotiation process invoked via the ibm,client-architecture-support OF
call. Its only caller is h_client_architecture_support() which handles
most of the rest of that process.
I believe it was placed in a separate file originally to handle some
fiddly dependencies between functions, but mostly it's just confusing
to have the CAS process split into two pieces like this. Now that
compose response is simplified (by just generating the whole device
tree anew), it's cleaner to just fold it into
h_client_architecture_support().
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cedric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: d1d32d6255a395eb071c10aeffb932a3485bdfcd
https://github.com/qemu/qemu/commit/d1d32d6255a395eb071c10aeffb932a3485bdfcd
Author: David Gibson <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_ovec.c
M include/hw/ppc/spapr_ovec.h
Log Message:
-----------
spapr: Simplify ovec diff
spapr_ovec_diff(ov, old, new) has somewhat complex semantics. ov is set
to those bits which are in new but not old, and it returns as a boolean
whether or not there are any bits in old but not new.
It turns out that both callers only care about the second, not the first.
This is basically equivalent to a bitmap subset operation, which is easier
to understand and implement. So replace spapr_ovec_diff() with
spapr_ovec_subset().
Cc: Mike Roth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cedric Le Goater <address@hidden>
Commit: 401774387aeb37f2ada9bb18f7c7e307b21a3e93
https://github.com/qemu/qemu/commit/401774387aeb37f2ada9bb18f7c7e307b21a3e93
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/ppc.c
M include/hw/ppc/ppc.h
M target/ppc/translate_init.inc.c
Log Message:
-----------
ppc: Deassert the external interrupt pin in KVM on reset
When a CPU is reset, QEMU makes sure no interrupt is pending by clearing
CPUPPCstate::pending_interrupts in ppc_cpu_reset(). In the case of a
complete machine emulation, eg. a sPAPR machine, an external interrupt
request could still be pending in KVM though, eg. an IPI. It will be
eventually presented to the guest, which is supposed to acknowledge it at
the interrupt controller. If the interrupt controller is emulated in QEMU,
either XICS or XIVE, ppc_set_irq() won't deassert the external interrupt
pin in KVM since it isn't pending anymore for QEMU. When the vCPU re-enters
the guest, the interrupt request is still pending and the vCPU will try
again to acknowledge it. This causes an infinite loop and eventually hangs
the guest.
The code has been broken since the beginning. The issue wasn't hit before
because accel=kvm,kernel-irqchip=off is an awkward setup that never got
used until recently with the LC92x IBM systems (aka, Boston).
Add a ppc_irq_reset() function to do the necessary cleanup, ie. deassert
the IRQ pins of the CPU in QEMU and most importantly the external interrupt
pin for this vCPU in KVM.
Reported-by: Satheesh Rajendran <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 4febcdd88f08422a66a1aa0dc55e1472abed3c4b
https://github.com/qemu/qemu/commit/4febcdd88f08422a66a1aa0dc55e1472abed3c4b
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/xics.c
Log Message:
-----------
xics: Don't deassert outputs
The correct way to do this is to deassert the input pins on the CPU side.
This is the case since a previous change.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c1ad0b892ce20cf2b5e619c79e8a0c4c66b235dc
https://github.com/qemu/qemu/commit/c1ad0b892ce20cf2b5e619c79e8a0c4c66b235dc
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/ppc.c
M target/ppc/cpu.h
Log Message:
-----------
ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU models
The power7_set_irq() and power9_set_irq() functions set this but it is
never used actually. Modern Book3s compatible CPUs are only supported
by the pnv and spapr machines. They have an interrupt controller, XICS
for POWER7/8 and XIVE for POWER9, whose models don't require to track
IRQ input states at the CPU level.
Drop these lines to avoid confusion.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6d38666a8931ef6d92535df9d977f2fcba880d2b
https://github.com/qemu/qemu/commit/6d38666a8931ef6d92535df9d977f2fcba880d2b
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M target/ppc/helper_regs.h
Log Message:
-----------
ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVM
This only makes sense with an emulated CPU. Don't set the bit in
CPUState::interrupt_request when using KVM to avoid confusions.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2b6dda81c327239af1643063d4c13a3134425710
https://github.com/qemu/qemu/commit/2b6dda81c327239af1643063d4c13a3134425710
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M target/ppc/cpu.h
Log Message:
-----------
ppc: Make PPCVirtualHypervisor an incomplete type
PPCVirtualHypervisor is an interface instance. It should never be
dereferenced. Drop the dummy type definition for extra safety, which
is the common practice with QOM interfaces.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 7d37b274ffd382d1d9e46164eca557b5f87383aa
https://github.com/qemu/qemu/commit/7d37b274ffd382d1d9e46164eca557b5f87383aa
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M target/ppc/compat.c
M target/ppc/cpu-models.c
M target/ppc/cpu-models.h
M target/ppc/cpu.h
M target/ppc/translate_init.inc.c
Log Message:
-----------
target/ppc: Add POWER10 DD1.0 model information
This includes in QEMU a new CPU model for the POWER10 processor with
the same capabilities of a POWER9 process. The model will be extended
when support is completed.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2b548a4255ca07cf4d467b7fb3bdf2ab79b7dff5
https://github.com/qemu/qemu/commit/2b548a4255ca07cf4d467b7fb3bdf2ab79b7dff5
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M hw/ppc/pnv_xscom.c
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machine
This is an empty shell with the XSCOM bus and cores. The chip controllers
will come later.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c5412b1d28535f8a2c252c9b62634389b83cae48
https://github.com/qemu/qemu/commit/c5412b1d28535f8a2c252c9b62634389b83cae48
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv_psi.c
Log Message:
-----------
ppc/psi: cleanup definitions
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 8b50ce850538223b8dd2c2f4ed8a819d3c60bfc1
https://github.com/qemu/qemu/commit/8b50ce850538223b8dd2c2f4ed8a819d3c60bfc1
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_psi.c
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_psi.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: add a PSI bridge model for POWER10
The POWER10 PSIHB controller is very similar to the one on POWER9. We
should probably introduce a common PnvPsiXive object.
The ESB page size should be changed to 64k when P10 support is ready.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2661f6ab2ba1694d7c19efdd622378817cb874ea
https://github.com/qemu/qemu/commit/2661f6ab2ba1694d7c19efdd622378817cb874ea
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_lpc.c
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_lpc.h
Log Message:
-----------
ppc/pnv: add a LPC Controller model for POWER10
Same a POWER9, only the MMIO window changes.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5d62725b2fefd59abf7225d620f7092fd34b8e11
https://github.com/qemu/qemu/commit/5d62725b2fefd59abf7225d620f7092fd34b8e11
Author: Suraj Jitindar Singh <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/ppc.c
M include/hw/ppc/ppc.h
M linux-user/ppc/cpu_loop.c
M target/ppc/cpu.h
M target/ppc/helper.h
M target/ppc/timebase_helper.c
M target/ppc/translate_init.inc.c
Log Message:
-----------
target/ppc: Implement the VTB for HV access
The virtual timebase register (VTB) is a 64-bit register which
increments at the same rate as the timebase register, present on POWER8
and later processors.
The register is able to be read/written by the hypervisor and read by
the supervisor. All other accesses are illegal.
Currently the VTB is just an alias for the timebase (TB) register.
Implement the VTB so that is can be read/written independent of the TB.
Make use of the existing method for accessing timebase facilities where
by the compensation is stored and used to compute the value on reads/is
updated on writes.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
[ clg: rebased on current ppc tree ]
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5cc7e69f6da5c52a0ac9f48ace40caf91fce807d
https://github.com/qemu/qemu/commit/5cc7e69f6da5c52a0ac9f48ace40caf91fce807d
Author: Suraj Jitindar Singh <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/ppc.c
M include/hw/ppc/ppc.h
M target/ppc/cpu.h
M target/ppc/helper.h
M target/ppc/timebase_helper.c
M target/ppc/translate_init.inc.c
Log Message:
-----------
target/ppc: Work [S]PURR implementation and add HV support
The Processor Utilisation of Resources Register (PURR) and Scaled
Processor Utilisation of Resources Register (SPURR) provide an estimate
of the resources used by the thread, present on POWER7 and later
processors.
Currently the [S]PURR registers simply count at the rate of the
timebase.
Preserve this behaviour but rework the implementation to store an offset
like the timebase rather than doing the calculation manually. Also allow
hypervisor write access to the register along with the currently
available read access.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[ clg: rebased on current ppc tree ]
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 32d0f0d8de37519bcaa720c41f0f693b66016f1b
https://github.com/qemu/qemu/commit/32d0f0d8de37519bcaa720c41f0f693b66016f1b
Author: Suraj Jitindar Singh <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M target/ppc/cpu.h
M target/ppc/translate_init.inc.c
Log Message:
-----------
target/ppc: Add SPR ASDR
The Access Segment Descriptor Register (ASDR) provides information about
the storage element when taking a hypervisor storage interrupt. When
performing nested radix address translation, this is normally the guest
real address. This register is present on POWER9 processors and later.
Implement the ADSR, note read and write access is limited to the
hypervisor.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f0ec31b1e21718b728753bcbfad54862a587050f
https://github.com/qemu/qemu/commit/f0ec31b1e21718b728753bcbfad54862a587050f
Author: Suraj Jitindar Singh <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/ppc.c
M target/ppc/cpu.h
M target/ppc/helper.h
M target/ppc/timebase_helper.c
M target/ppc/translate_init.inc.c
Log Message:
-----------
target/ppc: Add SPR TBU40
The spr TBU40 is used to set the upper 40 bits of the timebase
register, present on POWER5+ and later processors.
This register can only be written by the hypervisor, and cannot be read.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 109dce37860aeb0e8894cb36b29d40f279c6bb6b
https://github.com/qemu/qemu/commit/109dce37860aeb0e8894cb36b29d40f279c6bb6b
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv_xscom.c
Log Message:
-----------
ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodes
Some PnvXScomInterface objects lie a bit deeper (PnvPBCQState) than
the first layer, so we need to loop on the whole object hierarchy to
catch them.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
[dwg: Corrected error in comment]
Signed-off-by: David Gibson <address@hidden>
Commit: 9e028fffaabee37ea05baf1950376f401bbff91c
https://github.com/qemu/qemu/commit/9e028fffaabee37ea05baf1950376f401bbff91c
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv_xscom.c
Log Message:
-----------
ppc/pnv: populate the DT with realized XSCOM devices
Some devices could be initialized in the instance_init handler but not
realized for configuration reasons. Nodes should not be added in the DT
for such devices.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 90cce00c7be29f040be89c0f910336dd25b268fa
https://github.com/qemu/qemu/commit/90cce00c7be29f040be89c0f910336dd25b268fa
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: Make PnvXScomInterface an incomplete type
PnvXScomInterface is an interface instance. It should never be
dereferenced. Drop the dummy type definition for extra safety,
which is the common practice with QOM interfaces.
While here also convert the bogus OBJECT_CHECK() to INTERFACE_CHECK().
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 8f09231631c7b92b7abb6b807e6994d04ff3cb17
https://github.com/qemu/qemu/commit/8f09231631c7b92b7abb6b807e6994d04ff3cb17
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_homer.c
M hw/ppc/pnv_xscom.c
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_homer.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: Introduce PBA registers
The PBA bridge unit (Power Bus Access) connects the OCC (On Chip
Controller) to the Power bus and System Memory. The PBA is used to
gather sensor data, for power management, for sleep states, for
initial boot, among other things.
The PBA logic provides a set of four registers PowerBus Access Base
Address Registers (PBABAR0..3) which map the OCC address space to the
PowerBus space. These registers are setup by the initial FW and define
the PowerBus Range of system memory that can be accessed by PBA.
The current modeling of the PBABAR registers is done under the common
XSCOM handlers. We introduce a specific XSCOM regions for these
registers and fix :
- BAR sizes and BAR masks
- The mapping of the OCC common area. It is common to all chips and
should be mapped once. We will address per-OCC area in the next
change.
- OCC common area is in BAR 3 on P8
Inspired by previous work of Balamuruhan S <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3a1b70b66b5cb45abce10a57826fde1eb58827c7
https://github.com/qemu/qemu/commit/3a1b70b66b5cb45abce10a57826fde1eb58827c7
Author: Cédric Le Goater <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_occ.c
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_occ.h
Log Message:
-----------
ppc/pnv: Fix OCC common area region mapping
The OCC common area is mapped at a unique address on the system and
each OCC is assigned a segment to expose its sensor data :
-------------------------------------------------------------------------
| Start (Offset from | End | Size |Description |
| BAR2 base address) | | | |
-------------------------------------------------------------------------
| 0x00580000 | 0x005A57FF |150kB |OCC 0 Sensor Data Block|
| 0x005A5800 | 0x005CAFFF |150kB |OCC 1 Sensor Data Block|
| : | : | : | : |
| 0x00686800 | 0x006ABFFF |150kB |OCC 7 Sensor Data Block|
| 0x006AC000 | 0x006FFFFF |336kB |Reserved |
-------------------------------------------------------------------------
Maximum size is 1.5MB.
We could define a "OCC common area" memory region at the machine level
and sub regions for each OCC. But it adds some extra complexity to the
models. Fix the current layout with a simpler model.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: aeb7a330f46ba530b40d7be5a3dce44e552f79a9
https://github.com/qemu/qemu/commit/aeb7a330f46ba530b40d7be5a3dce44e552f79a9
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M include/hw/ppc/pnv_xscom.h
M include/hw/ppc/spapr_vio.h
Log Message:
-----------
ppc: Drop useless extern annotation for functions
Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 41c4ef7009adb3d7c4f252656bb6b18080f7c3a2
https://github.com/qemu/qemu/commit/41c4ef7009adb3d7c4f252656bb6b18080f7c3a2
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv_psi.c
M include/hw/ppc/pnv_psi.h
Log Message:
-----------
ppc/pnv: Introduce PnvPsiClass::compat
The Processor Service Interface (PSI) model has a chip_type class level
attribute, which is used to generate the content of the "compatible" DT
property according to the CPU type.
Since the PSI model already has specialized classes for each supported
CPU type, it seems cleaner to achieve this with QOM. Provide the content
of the "compatible" property with a new class level attribute.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 248e4e924e873ffb36e9af725281f20614c58062
https://github.com/qemu/qemu/commit/248e4e924e873ffb36e9af725281f20614c58062
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv_psi.c
M include/hw/ppc/pnv_psi.h
Log Message:
-----------
ppc/pnv: Drop PnvPsiClass::chip_type
It isn't used anymore.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d76f2da7a5b6330fba70f2c14f209de92e26abab
https://github.com/qemu/qemu/commit/d76f2da7a5b6330fba70f2c14f209de92e26abab
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compat
The pnv_dt_create() function generates different contents for the
"compatible" property of the root node in the DT, depending on the
CPU type. This is open coded with multiple ifs using pnv_is_powerXX()
helpers.
It seems cleaner to achieve with QOM. Introduce a base class for the
powernv machine and a compat attribute that each child class can use
to provide the value for the "compatible" property.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
[dwg: Folded in small fix Greg spotted after posting]
Signed-off-by: David Gibson <address@hidden>
Commit: 7a90c6a1b650e3cd6391543cdf6587c5bc9f28c1
https://github.com/qemu/qemu/commit/7a90c6a1b650e3cd6391543cdf6587c5bc9f28c1
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Introduce PnvMachineClass::dt_power_mgt()
We add an extra node to advertise power management on some machines,
namely powernv9 and powernv10. This is achieved by using the
pnv_is_power9() and pnv_is_power10() helpers.
This can be achieved with QOM. Add a method to the base class for
powernv machines and have it implemented by machine types that
support power management instead.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: acc39abb311d75d945c0efb17ae43bf3ef367170
https://github.com/qemu/qemu/commit/acc39abb311d75d945c0efb17ae43bf3ef367170
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpers
They aren't used anymore.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 85913070a6c9fcbe1ac6a043f3278b2982702143
https://github.com/qemu/qemu/commit/85913070a6c9fcbe1ac6a043f3278b2982702143
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Introduce PnvChipClass::intc_print_info() method
The pnv_pic_print_info() callback checks the type of the chip in order
to forward to the request appropriate interrupt controller. This can
be achieved with QOM. Introduce a method for this in the base chip class
and implement it in child classes.
This also prepares ground for the upcoming interrupt controller of POWER10
chips.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c4b2c40c0eea3bc8ad286a6a1a62209c4bc332e3
https://github.com/qemu/qemu/commit/c4b2c40c0eea3bc8ad286a6a1a62209c4bc332e3
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Introduce PnvChipClass::xscom_core_base() method
The pnv_chip_core_realize() function configures the XSCOM MMIO subregion
for each core of a single chip. The base address of the subregion depends
on the CPU type. Its computation is currently open-code using the
pnv_chip_is_powerXX() helpers. This can be achieved with QOM. Introduce
a method for this in the base chip class and implement it in child classes.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3f5b45ca4f95a65a5164b3219c7fec64eff08638
https://github.com/qemu/qemu/commit/3f5b45ca4f95a65a5164b3219c7fec64eff08638
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_xscom.c
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom()
Since pnv_dt_xscom() is called from chip specific dt_populate() hooks,
it shouldn't have to guess the chip type in order to populate the "reg"
property. Just pass the base address and address size as arguments.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c396c58a02f16af7b44448a39f61ebf0af7b95b5
https://github.com/qemu/qemu/commit/c396c58a02f16af7b44448a39f61ebf0af7b95b5
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_xscom.c
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: Pass content of the "compatible" property to pnv_dt_xscom()
Since pnv_dt_xscom() is called from chip specific dt_populate() hooks,
it shouldn't have to guess the chip type in order to populate the
"compatible" property. Just pass the compat string and its size as
arguments.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3caf7bd0a2874717c5cf052a9840efe9c7774f2e
https://github.com/qemu/qemu/commit/3caf7bd0a2874717c5cf052a9840efe9c7774f2e
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpers
They aren't used anymore.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 70c059e9266fc7d79e40c9d297722ccb717ec386
https://github.com/qemu/qemu/commit/70c059e9266fc7d79e40c9d297722ccb717ec386
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_xscom.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Introduce PnvChipClass::xscom_pcba() method
The XSCOM bus is implemented with a QOM interface, which is mostly
generic from a CPU type standpoint, except for the computation of
addresses on the Pervasive Connect Bus (PCB) network. This is handled
by the pnv_xscom_pcba() function with a switch statement based on
the chip_type class level attribute of the CPU chip.
This can be achieved using QOM. Also the address argument is masked with
PNV_XSCOM_SIZE - 1, which is for POWER8 only. Addresses may have different
sizes with other CPU types. Have each CPU chip type handle the appropriate
computation with a QOM xscom_pcba() method.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5084c8b76365f4570520e2cb549089ad523dc953
https://github.com/qemu/qemu/commit/5084c8b76365f4570520e2cb549089ad523dc953
Author: Greg Kurz <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Drop PnvChipClass::type
It isn't used anymore.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a363e9ed8731f45674260932a340a0d81c4b0a6f
https://github.com/qemu/qemu/commit/a363e9ed8731f45674260932a340a0d81c4b0a6f
Author: Alexey Kardashevskiy <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
Log Message:
-----------
pseries: Update SLOF firmware image
This fixes PCI bridges support regression.
This enables IOMMU support in virtio drivers.
The full list of changes is:
Alexey Kardashevskiy (12):
allocator: Fix format strings for DEBUG
virtio: Make virtio_set_qaddr static
client: Load initramdisk location
sloffs: Fix -Wunused-result gcc warnings in read/write
pci-phb: Reimplement dma-map-in/out
virtio: Store queue descriptors in virtio_device
virtio-net: Init queues after features negotiation
virtio: Enable IOMMU
ibm,client-architecture-support: Fix stack handling
fdt: Fix updating the tree at H_CAS
version: update to 20191206
version: update to 20191217
Michael Roth (1):
dma: Define default dma methods for using by client/package instances
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 98ac38cd5ad5e9496277c943020bc4bf16adf10b
https://github.com/qemu/qemu/commit/98ac38cd5ad5e9496277c943020bc4bf16adf10b
Author: Peter Maydell <address@hidden>
Date: 2019-12-17 (Tue, 17 Dec 2019)
Changed paths:
M hw/intc/pnv_xive.c
M hw/intc/spapr_xive.c
M hw/intc/spapr_xive_kvm.c
M hw/intc/xics.c
M hw/intc/xics_kvm.c
M hw/intc/xics_spapr.c
M hw/intc/xive.c
M hw/ipmi/ipmi_bmc_sim.c
M hw/ppc/Makefile.objs
M hw/ppc/pnv.c
M hw/ppc/pnv_bmc.c
M hw/ppc/pnv_core.c
M hw/ppc/pnv_homer.c
M hw/ppc/pnv_lpc.c
M hw/ppc/pnv_occ.c
A hw/ppc/pnv_pnor.c
M hw/ppc/pnv_psi.c
M hw/ppc/pnv_xscom.c
M hw/ppc/ppc.c
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_irq.c
M hw/ppc/spapr_ovec.c
M include/hw/ipmi/ipmi.h
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_homer.h
M include/hw/ppc/pnv_lpc.h
M include/hw/ppc/pnv_occ.h
A include/hw/ppc/pnv_pnor.h
M include/hw/ppc/pnv_psi.h
M include/hw/ppc/pnv_xive.h
M include/hw/ppc/pnv_xscom.h
M include/hw/ppc/ppc.h
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_irq.h
M include/hw/ppc/spapr_ovec.h
M include/hw/ppc/spapr_vio.h
M include/hw/ppc/spapr_xive.h
M include/hw/ppc/xics_spapr.h
M include/hw/ppc/xive.h
M include/hw/ppc/xive_regs.h
M include/standard-headers/linux/ethtool.h
M include/standard-headers/linux/virtio_ring.h
M linux-headers/asm-arm/kvm.h
M linux-headers/asm-arm64/kvm.h
M linux-headers/asm-mips/unistd_n32.h
M linux-headers/asm-mips/unistd_n64.h
M linux-headers/asm-mips/unistd_o32.h
M linux-headers/asm-powerpc/kvm.h
M linux-headers/linux/kvm.h
M linux-headers/linux/psp-sev.h
M linux-user/ppc/cpu_loop.c
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
M target/ppc/compat.c
M target/ppc/cpu-models.c
M target/ppc/cpu-models.h
M target/ppc/cpu.h
M target/ppc/helper.h
M target/ppc/helper_regs.h
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
M target/ppc/timebase_helper.c
M target/ppc/translate_init.inc.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20191217' into
staging
ppc patch queue 2019-12-17
This is the first pull request for the qemu-5.0 branch. It has a lot
of accumulated changes, including:
* SLOF update to support boot using the IOMMU (will become
necessary for secure guests)
* Clean ups to pnv handling of chip models
* A number of extensions to the powernv machine model
* TCG extensions to allow powernv emulated systems to run KVM guests
* Outline support for POWER10 chips in powernv
* Cleanups to the ibm,client-architecture-support feature negotiation path
* XIVE reworks to better handle the powernv machine
* Improvements to not waste interrupt queues and other semi-scarce
resources when using XIVE under KVM
# gpg: Signature made Tue 17 Dec 2019 04:42:20 GMT
# gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>" [full]
# gpg: aka "David Gibson (Red Hat) <address@hidden>" [full]
# gpg: aka "David Gibson (ozlabs.org) <address@hidden>" [full]
# gpg: aka "David Gibson (kernel.org) <address@hidden>"
[unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-5.0-20191217: (88 commits)
pseries: Update SLOF firmware image
ppc/pnv: Drop PnvChipClass::type
ppc/pnv: Introduce PnvChipClass::xscom_pcba() method
ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpers
ppc/pnv: Pass content of the "compatible" property to pnv_dt_xscom()
ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom()
ppc/pnv: Introduce PnvChipClass::xscom_core_base() method
ppc/pnv: Introduce PnvChipClass::intc_print_info() method
ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpers
ppc/pnv: Introduce PnvMachineClass::dt_power_mgt()
ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compat
ppc/pnv: Drop PnvPsiClass::chip_type
ppc/pnv: Introduce PnvPsiClass::compat
ppc: Drop useless extern annotation for functions
ppc/pnv: Fix OCC common area region mapping
ppc/pnv: Introduce PBA registers
ppc/pnv: Make PnvXScomInterface an incomplete type
ppc/pnv: populate the DT with realized XSCOM devices
ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodes
target/ppc: Add SPR TBU40
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/e98e5c35d8d9...98ac38cd5ad5
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