[Qemu-commits] [qemu/qemu] 77b168: i386: Add MSR feature bit for MDS-NO

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 77b168d221191156c47fcd8d1c47329dfdb9439e
      
https://github.com/qemu/qemu/commit/77b168d221191156c47fcd8d1c47329dfdb9439e
  Author: Cathy Zhang <address@hidden>
  Date:   2019-12-13 (Fri, 13 Dec 2019)

  Changed paths:
    M target/i386/cpu.h

  Log Message:
  -----------
  i386: Add MSR feature bit for MDS-NO

Define MSR_ARCH_CAP_MDS_NO in the IA32_ARCH_CAPABILITIES MSR to allow
CPU models to report the feature when host supports it.

Signed-off-by: Cathy Zhang <address@hidden>
Reviewed-by: Xiaoyao Li <address@hidden>
Reviewed-by: Tao Xu <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 5af514d0cb314f43bc53f2aefb437f6451d64d0c
      
https://github.com/qemu/qemu/commit/5af514d0cb314f43bc53f2aefb437f6451d64d0c
  Author: Cathy Zhang <address@hidden>
  Date:   2019-12-13 (Fri, 13 Dec 2019)

  Changed paths:
    M target/i386/cpu.h

  Log Message:
  -----------
  i386: Add macro for stibp

stibp feature is already added through the following commit.
https://github.com/qemu/qemu/commit/0e8916582991b9fd0b94850a8444b8b80d0a0955

Add a macro for it to allow CPU models to report it when host supports.

Signed-off-by: Cathy Zhang <address@hidden>
Reviewed-by: Xiaoyao Li <address@hidden>
Reviewed-by: Tao Xu <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 22a866b6166db5caa4abaa6e656c2a431fa60726
      
https://github.com/qemu/qemu/commit/22a866b6166db5caa4abaa6e656c2a431fa60726
  Author: Cathy Zhang <address@hidden>
  Date:   2019-12-13 (Fri, 13 Dec 2019)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: Add new CPU model Cooperlake

Cooper Lake is intel's successor to Cascade Lake, the new
CPU model inherits features from Cascadelake-Server, while
add one platform associated new feature: AVX512_BF16. Meanwhile,
add STIBP for speculative execution.

Signed-off-by: Cathy Zhang <address@hidden>
Reviewed-by: Xiaoyao Li <address@hidden>
Reviewed-by: Tao Xu <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Bruce Rogers <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 88703ce2e6bbc8cc00c90c1bb8af1f3cd964ac9c
      
https://github.com/qemu/qemu/commit/88703ce2e6bbc8cc00c90c1bb8af1f3cd964ac9c
  Author: Eduardo Habkost <address@hidden>
  Date:   2019-12-13 (Fri, 13 Dec 2019)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: Use g_autofree in a few places

Get rid of 12 explicit g_free() calls.

Signed-off-by: Eduardo Habkost <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Stefano Garzarella <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: e98e5c35d8d9b83186f8d697afd68113abbac736
      
https://github.com/qemu/qemu/commit/e98e5c35d8d9b83186f8d697afd68113abbac736
  Author: Peter Maydell <address@hidden>
  Date:   2019-12-17 (Tue, 17 Dec 2019)

  Changed paths:
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' 
into staging

x86 queue, 2019-12-16

Feature:
* Cooperlake CPU model

Cleanups:
* Use g_autofree in a few places

# gpg: Signature made Mon 16 Dec 2019 19:36:51 GMT
# gpg:                using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Eduardo Habkost <address@hidden>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-next-pull-request:
  i386: Use g_autofree in a few places
  i386: Add new CPU model Cooperlake
  i386: Add macro for stibp
  i386: Add MSR feature bit for MDS-NO

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/cb88904a5490...e98e5c35d8d9