[Qemu-commits] [qemu/qemu] fad189: spapr/rtas: Force big endian compile for rtas

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: fad189d1f6c2919dbde5433c6c15548eefef75e8
      
https://github.com/qemu/qemu/commit/fad189d1f6c2919dbde5433c6c15548eefef75e8
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M pc-bios/spapr-rtas/Makefile

  Log Message:
  -----------
  spapr/rtas: Force big endian compile for rtas

At the moment the rtas's Makefile uses generic QEMU rules which means
that when QEMU is compiled on a little endian system, the spapr-rtas.bin
is compiled as little endian too which is incorrect as it is always
executed in big endian mode.

This enforces -mbig by defining %.o:%.S rule as spapr-rtas.bin is
a standalone guest binary which should not depend on QEMU flags anyway.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b87a0100cde349a977a19969660660bcb84720be
      
https://github.com/qemu/qemu/commit/b87a0100cde349a977a19969660660bcb84720be
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M docs/specs/ppc-spapr-xive.rst
    M docs/specs/ppc-xive.rst

  Log Message:
  -----------
  docs: updates on the POWER9 XIVE interrupt controller documentation

This includes various small updates and a better description of the
chosen interrupt mode resulting from the combination of the 'ic-mode'
machine option, the 'kernel_irqchip' option, guest support and KVM
support.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: e1a9b7d1fcc1f41c917c0306bd1f2adf0d5d8e1e
      
https://github.com/qemu/qemu/commit/e1a9b7d1fcc1f41c917c0306bd1f2adf0d5d8e1e
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/intc/pnv_xive.c

  Log Message:
  -----------
  ppc/pnv: fix StoreEOI activation

The firmware (skiboot) of the PowerNV machines can configure the XIVE
interrupt controller to activate StoreEOI on the ESB pages of the
interrupts. This feature lets software do an EOI with a store instead
of a load. It is not activated today on P9 for rare race condition
issues but it should be on future processors.

Nevertheless, QEMU has a model for StoreEOI which can be used today by
experimental firmwares. But, the use of object_property_set_int() in
the PnvXive model is incorrect and crashes QEMU. Replace it with a
direct access to the ESB flags of the XiveSource object modeling the
internal sources of the interrupt controller.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 709044fd2da7797ae9f60088b832af085542eda6
      
https://github.com/qemu/qemu/commit/709044fd2da7797ae9f60088b832af085542eda6
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/ppc/pnv.c
    M hw/ppc/pnv_xscom.c
    M include/hw/ppc/pnv.h
    M include/hw/ppc/pnv_xscom.h

  Log Message:
  -----------
  ppc/pnv: fix XSCOM MMIO base address for P9 machines with multiple chips

The PNV_XSCOM_BASE and PNV_XSCOM_SIZE macros are specific to POWER8
and they are used when the device tree is populated and the MMIO
region created, even for POWER9 chips. This is not too much of a
problem today because we don't have important devices on the second
chip, but we might have oneday (PHBs).

Fix by using the appropriate macros in case of P9.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: c29a0b0fb3520a2ab5fe566bf39340b4ef3efeb9
      
https://github.com/qemu/qemu/commit/c29a0b0fb3520a2ab5fe566bf39340b4ef3efeb9
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/ppc/pnv.c
    M include/hw/ppc/pnv.h

  Log Message:
  -----------
  ppc/pnv: remove xscom_base field from PnvChip

It has now became useless with the previous patch.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 740a19313b85527f6984b0fd4fee9b683b4ea1e2
      
https://github.com/qemu/qemu/commit/740a19313b85527f6984b0fd4fee9b683b4ea1e2
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/ppc/spapr_pci.c

  Log Message:
  -----------
  spapr_pci: Fix potential NULL pointer dereference in spapr_dt_pci_bus()

Commit 14e714900f6 refactored the call to spapr_dt_drc(),
introducing a potential NULL pointer dereference while
accessing bus->parent_dev.
A trivial audit show 'bus' is not null in the two places
the static function spapr_dt_drc() is called.

Since the 'bus' parameter is not NULL in both callers, remove
remove the test on if (bus), and add an assert() to silent
static analyzers.

This fixes:

  /hw/ppc/spapr_pci.c: 1367 in spapr_dt_pci_bus()
  >>>     CID 1401933:  Null pointer dereferences  (FORWARD_NULL)
  >>>     Dereferencing null pointer "bus".
  1367         ret = spapr_dt_drc(fdt, offset, OBJECT(bus->parent_dev),
  1368                            SPAPR_DR_CONNECTOR_TYPE_PCI);

Fixes: 14e714900f6
Reported-by: Coverity (CID 1401933)
Suggested-by: Greg Kurz <address@hidden>
Suggested-by: David Gibson <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d9715d67722ebd7198a35681cfc9a6595bdb08f0
      
https://github.com/qemu/qemu/commit/d9715d67722ebd7198a35681cfc9a6595bdb08f0
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/intc/xics_spapr.c

  Log Message:
  -----------
  xics/spapr: Prevent RTAS/hypercalls emulation to be used by in-kernel XICS

The XICS-related RTAS calls and hypercalls in QEMU are not supposed to
be called when the KVM in-kernel XICS is in use.

Add some explicit checks to detect that, print an error message and report
an hardware error to the guest.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
[dwg: Correction to commit message]
Signed-off-by: David Gibson <address@hidden>


  Commit: d9293c4843b2503c905d35899077fc415824783e
      
https://github.com/qemu/qemu/commit/d9293c4843b2503c905d35899077fc415824783e
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/intc/xics_kvm.c
    M hw/intc/xics_spapr.c
    M hw/ppc/spapr_irq.c
    M include/hw/ppc/spapr.h
    M include/hw/ppc/xics.h
    M include/hw/ppc/xics_spapr.h

  Log Message:
  -----------
  xics/spapr: Register RTAS/hypercalls once at machine init

QEMU may crash when running a spapr machine in 'dual' interrupt controller
mode on some older (but not that old, eg. ubuntu 18.04.2) KVMs with partial
XIVE support:

qemu-system-ppc64: hw/ppc/spapr_rtas.c:411: spapr_rtas_register:
 Assertion `!name || !rtas_table[token].name' failed.

XICS is controlled by the guest thanks to a set of RTAS calls. Depending
on whether KVM XICS is used or not, the RTAS calls are handled by KVM or
QEMU. In both cases, QEMU needs to expose the RTAS calls to the guest
through the "rtas" node of the device tree.

The spapr_rtas_register() helper takes care of all of that: it adds the
RTAS call token to the "rtas" node and registers a QEMU callback to be
invoked when the guest issues the RTAS call. In the KVM XICS case, QEMU
registers a dummy callback that just prints an error since it isn't
supposed to be invoked, ever.

Historically, the XICS controller was setup during machine init and
released during final teardown. This changed when the 'dual' interrupt
controller mode was added to the spapr machine: in this case we need
to tear the XICS down and set it up again during machine reset. The
crash happens because we indeed have an incompatibility with older
KVMs that forces QEMU to fallback on emulated XICS, which tries to
re-registers the same RTAS calls.

This could be fixed by adding proper rollback that would unregister
RTAS calls on error. But since the emulated RTAS calls in QEMU can
now detect when they are mistakenly called while KVM XICS is in
use, it seems simpler to register them once and for all at machine
init. This fixes the crash and allows to remove some now useless
lines of code.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 7abc0c6d35306a41a48eda7ab2b7b2d51f32f86b
      
https://github.com/qemu/qemu/commit/7abc0c6d35306a41a48eda7ab2b7b2d51f32f86b
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M docs/specs/ppc-spapr-xive.rst
    M hw/intc/xics_kvm.c
    M hw/ppc/spapr_irq.c
    M include/hw/ppc/xics_spapr.h

  Log Message:
  -----------
  xics/spapr: Detect old KVM XICS on POWER9 hosts

Older KVMs on POWER9 don't support destroying/recreating a KVM XICS
device, which is required by 'dual' interrupt controller mode. This
causes QEMU to emit a warning when the guest is rebooted and to fall
back on XICS emulation:

qemu-system-ppc64: warning: kernel_irqchip allowed but unavailable:
 Error on KVM_CREATE_DEVICE for XICS: File exists

If kernel irqchip is required, QEMU will thus exit when the guest is
first rebooted. Failing QEMU this late may be a painful experience
for the user.

Detect that and exit at machine init instead.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 7701aeed0f0162fe9f6d1bb1ccba158b55a2ded4
      
https://github.com/qemu/qemu/commit/7701aeed0f0162fe9f6d1bb1ccba158b55a2ded4
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M target/ppc/kvm.c

  Log Message:
  -----------
  target/ppc: fix compile error in kvmppc_define_rtas_kernel_token()

gcc9 reports :

In file included from /usr/include/string.h:494,
                 from ./include/qemu/osdep.h:101,
                 from ./target/ppc/kvm.c:17:
In function ‘strncpy’,
    inlined from ‘kvmppc_define_rtas_kernel_token’ at ./target/ppc/kvm.c:2648:5:
/usr/include/bits/string_fortified.h:106:10: error: ‘__builtin_strncpy’ 
specified bound 120 equals destination size [-Werror=stringop-truncation]
  106 |   return __builtin___strncpy_chk (__dest, __src, __len, __bos (__dest));
      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d9b9e6f6b91ed96d8e882d48ae83403b3a5c2b87
      
https://github.com/qemu/qemu/commit/d9b9e6f6b91ed96d8e882d48ae83403b3a5c2b87
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/intc/xics.c

  Log Message:
  -----------
  xics: Add comment about CPU hotplug

So that no one is tempted to drop that code, which is never called
for cold plugged CPUs.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: cf3b0334f2f94a6e5f6d9afed387c51aca775a1f
      
https://github.com/qemu/qemu/commit/cf3b0334f2f94a6e5f6d9afed387c51aca775a1f
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M target/ppc/fpu_helper.c

  Log Message:
  -----------
  target/ppc: remove getVSR()/putVSR() from fpu_helper.c

Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX
registers are in host endian order" functions getVSR() and putVSR() which used
to convert the VSR registers into host endian order are no longer required.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 2a17583082f5350edb17207d76252603ec960afa
      
https://github.com/qemu/qemu/commit/2a17583082f5350edb17207d76252603ec960afa
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M target/ppc/mem_helper.c

  Log Message:
  -----------
  target/ppc: remove getVSR()/putVSR() from mem_helper.c

Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX
registers are in host endian order" functions getVSR() and putVSR() which used
to convert the VSR registers into host endian order are no longer required.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 7e10b57dd9e0d2570ecccca0e2f418618f303d8c
      
https://github.com/qemu/qemu/commit/7e10b57dd9e0d2570ecccca0e2f418618f303d8c
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/ppc/spapr_pci.c

  Log Message:
  -----------
  spapr_pci: Fix DRC owner in spapr_dt_pci_bus()

spapr_dt_drc() scans the aliases of all DRConnector objects and filters
the ones that it will use to generate OF properties according to their
owner and type.

Passing bus->parent_dev _works_ if bus belongs to a PCI bridge, but it is
NULL if it is the PHB's root bus. This causes all allocated PCI DRCs to
be associated to all PHBs (visible in their "ibm,drc-types" properties).
As a consequence, hot unplugging a PHB results in PCI devices from the
other PHBs to be unplugged as well, and likely confuses the guest.

Use the same logic as in add_drcs() to ensure the correct owner is passed
to spapr_dt_drc().

Fixes: 14e714900f6b "spapr: Allow hot plug/unplug of PCI bridges and devices 
under PCI bridges"
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 25c79a3089cbaa624aa0d2d3c1b936f181041e1d
      
https://github.com/qemu/qemu/commit/25c79a3089cbaa624aa0d2d3c1b936f181041e1d
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/intc/xics_spapr.c

  Log Message:
  -----------
  xics/spapr: Only emulated XICS should use RTAS/hypercalls emulation

Checking that we're not using the in-kernel XICS is ok with the "xics"
interrupt controller mode, but it is definitely not enough with the
other modes since the guest could be using XIVE.

Ensure XIVE is not in use when emulated XICS RTAS/hypercalls are
called.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8d08fa93bb6054084c57607f99de5d5448748887
      
https://github.com/qemu/qemu/commit/8d08fa93bb6054084c57607f99de5d5448748887
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/ppc/spapr_pci.c

  Log Message:
  -----------
  spapr_pci: Drop useless CONFIG_KVM ifdefery

kvm_enabled() expands to (0) when CONFIG_KVM is not defined.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 7a660e776ea5bb90c4acc00645116a29b417fcdf
      
https://github.com/qemu/qemu/commit/7a660e776ea5bb90c4acc00645116a29b417fcdf
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/ppc/mac_oldworld.c

  Log Message:
  -----------
  hw/ppc/mac_oldworld: Drop useless CONFIG_KVM ifdefery

kvm_enabled() expands to (0) when CONFIG_KVM is not defined. It is
likely that the compiler will optimize the code out. And even if
it doesn't, we have a stub for kvmppc_get_hypercall().

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: da6e10177a3da496845f97929087581edff82b3b
      
https://github.com/qemu/qemu/commit/da6e10177a3da496845f97929087581edff82b3b
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/ppc/mac_newworld.c

  Log Message:
  -----------
  hw/ppc/mac_newworld: Drop useless CONFIG_KVM ifdefery

kvm_enabled() expands to (0) when CONFIG_KVM is not defined. The first
CONFIG_KVM guard is thus useless and it is likely that the compiler
will optimize the code out in the case of the second guard. And even
if it doesn't, we have a stub for kvmppc_get_hypercall().

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 6d893a4d7038abe88ae0123a9d805008ff7c1148
      
https://github.com/qemu/qemu/commit/6d893a4d7038abe88ae0123a9d805008ff7c1148
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/ppc/prep.c

  Log Message:
  -----------
  hw/ppc/prep: Drop useless CONFIG_KVM ifdefery

kvm_enabled() expands to (0) when CONFIG_KVM is not defined. It is
likely that the compiler will optimize the code out. And even if
it doesn't, we have a stub for kvmppc_get_hypercall().

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 363ce377da3e1d24094649a1c25065f5014fc6c9
      
https://github.com/qemu/qemu/commit/363ce377da3e1d24094649a1c25065f5014fc6c9
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/ppc/ppc.c

  Log Message:
  -----------
  hw/ppc: Drop useless CONFIG_KVM ifdefery

kvmppc_set_interrupt() has a stub that does nothing when CONFIG_KVM is
not defined.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 2fb4c6528ed82982c1c972799ad539709183bc7e
      
https://github.com/qemu/qemu/commit/2fb4c6528ed82982c1c972799ad539709183bc7e
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M include/hw/ppc/xics_spapr.h

  Log Message:
  -----------
  xics/spapr: Drop unused function declaration

Commit 9fb6eb7ca50c added the declaration of xics_spapr_connect(), which
has no implementation and no users.

This is a leftover from a previous iteration of this patch. Drop it.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: eab9f191a064913bb0011894143ed6053ecbdf69
      
https://github.com/qemu/qemu/commit/eab9f191a064913bb0011894143ed6053ecbdf69
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/intc/xics_kvm.c
    M hw/ppc/spapr_irq.c
    M include/hw/ppc/xics_spapr.h

  Log Message:
  -----------
  xics/spapr: Rename xics_kvm_init()

Switch to using the connect/disconnect terminology like we already do for
XIVE.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 64fb96214c4c0f107fa3b53878779217826b8f48
      
https://github.com/qemu/qemu/commit/64fb96214c4c0f107fa3b53878779217826b8f48
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/intc/xics_kvm.c

  Log Message:
  -----------
  xics/kvm: Skip rollback when KVM XICS is absent

There is no need to rollback anything at this point, so just return an
error.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: ab3d15fa84e49bdb509b7cf9f9c63e78298b2919
      
https://github.com/qemu/qemu/commit/ab3d15fa84e49bdb509b7cf9f9c63e78298b2919
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/intc/xics_kvm.c

  Log Message:
  -----------
  xics/kvm: Always use local_err in xics_kvm_init()

Passing both errp and &local_err to functions is a recipe for messing
things up.

Since we must use &local_err for icp_kvm_realize(), use &local_err
everywhere where rollback must happen and have a single call to
error_propagate() them all. While here, add errno to the error
message.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 330a21e3c45e9bee5f47e032b678a48e1ed84e9e
      
https://github.com/qemu/qemu/commit/330a21e3c45e9bee5f47e032b678a48e1ed84e9e
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/intc/xics.c
    M hw/intc/xics_kvm.c
    M include/hw/ppc/xics.h

  Log Message:
  -----------
  xics/kvm: Add error propagation to ic*_set_kvm_state() functions

This allows errors happening there to be propagated up to spapr_irq,
just like XIVE already does.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4812f261528898eef0030beee2270e23f98c6e05
      
https://github.com/qemu/qemu/commit/4812f261528898eef0030beee2270e23f98c6e05
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/intc/xics_kvm.c

  Log Message:
  -----------
  xics/kvm: Add proper rollback to xics_kvm_init()

Make xics_kvm_disconnect() able to undo the changes of a partial execution
of xics_kvm_connect() and use it to perform rollback.

Note that kvmppc_define_rtas_kernel_token(0) never fails, no matter the
RTAS call has been defined or not.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9723295a720ca26fe31a1e374555d83bccc051f4
      
https://github.com/qemu/qemu/commit/9723295a720ca26fe31a1e374555d83bccc051f4
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/ppc/ppc.c
    M target/ppc/kvm.c
    M target/ppc/kvm_ppc.h

  Log Message:
  -----------
  ppc: Introduce kvmppc_set_reg_tb_offset() helper

Introduce a KVM helper and its stub instead of guarding the code with
CONFIG_KVM.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 001d235c7edaa135faf94e2dd590c069af9c430e
      
https://github.com/qemu/qemu/commit/001d235c7edaa135faf94e2dd590c069af9c430e
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M target/ppc/kvm_ppc.h
    M target/ppc/machine.c

  Log Message:
  -----------
  target/ppc/machine: Add kvmppc_pvr_workaround_required() stub

This allows to drop the CONFIG_KVM guard from the code.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 03b32c092ea9b0d3a8d49586edf50a63f8ccffd9
      
https://github.com/qemu/qemu/commit/03b32c092ea9b0d3a8d49586edf50a63f8ccffd9
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M target/ppc/int_helper.c
    M target/ppc/internal.h

  Log Message:
  -----------
  target/ppc: remove getVSR()/putVSR() from int_helper.c

Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX
registers are in host endian order" functions getVSR() and putVSR() which used
to convert the VSR registers into host endian order are no longer required.

Now that there are now no more users of getVSR()/putVSR() these functions can
be completely removed.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 00084a25adf7d55f345453eabbad7c81b4e83955
      
https://github.com/qemu/qemu/commit/00084a25adf7d55f345453eabbad7c81b4e83955
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/translate/vsx-impl.inc.c

  Log Message:
  -----------
  target/ppc: introduce separate VSX_CMP macro for xvcmp* instructions

Rather than perform the VSR register decoding within the helper itself,
introduce a new VSX_CMP macro which performs the decode based upon xT, xA
and xB at translation time.

Subsequent commits will make the same changes for other instructions however
the xvcmp* instructions are different in that they return a set of flags to be
optionally written back to the crf[6] register. Move this logic from the
helper function to the generator function, along with the float_status update.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 99125c7499d1f7479e48340f622647e02f73da0f
      
https://github.com/qemu/qemu/commit/99125c7499d1f7479e48340f622647e02f73da0f
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/translate/vsx-impl.inc.c

  Log Message:
  -----------
  target/ppc: introduce GEN_VSX_HELPER_X3 macro to fpu_helper.c

Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_X3 macro which performs the decode based
upon xT, xA and xB at translation time.

With the previous changes to the VSX_CMP generator and helper macros the
opcode parameter is no longer required in the common case and can be
removed.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: e0d6a362be2172177f34eb0d9c8cb5118ee6607d
      
https://github.com/qemu/qemu/commit/e0d6a362be2172177f34eb0d9c8cb5118ee6607d
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/translate/vsx-impl.inc.c

  Log Message:
  -----------
  target/ppc: introduce separate generator and helper for xscvqpdp

Rather than perform the VSR register decoding within the helper itself,
introduce a new generator and helper function which perform the decode based
upon xT and xB at translation time.

The xscvqpdp helper is the only 2 parameter xT/xB implementation that requires
the opcode to be passed as an additional parameter, so handling this separately
allows us to optimise the conversion in the next commit.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 75cf84cbeeae9f33e6800ac78d41c3c6286fac06
      
https://github.com/qemu/qemu/commit/75cf84cbeeae9f33e6800ac78d41c3c6286fac06
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/translate/vsx-impl.inc.c

  Log Message:
  -----------
  target/ppc: introduce GEN_VSX_HELPER_X2 macro to fpu_helper.c

Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_X2 macro which performs the decode based
upon xT and xB at translation time.

With the previous change to the xscvqpdp generator and helper functions the
opcode parameter is no longer required in the common case and can be
removed.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 033e1fcd97babd6302fd7e983102966a2cafb95c
      
https://github.com/qemu/qemu/commit/033e1fcd97babd6302fd7e983102966a2cafb95c
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/translate/vsx-impl.inc.c

  Log Message:
  -----------
  target/ppc: introduce GEN_VSX_HELPER_X2_AB macro to fpu_helper.c

Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_X2_AB macro which performs the decode based
upon xA and xB at translation time.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8d830485fc551b4ff6f609e4245cf49e63fdf9ff
      
https://github.com/qemu/qemu/commit/8d830485fc551b4ff6f609e4245cf49e63fdf9ff
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/translate/vsx-impl.inc.c

  Log Message:
  -----------
  target/ppc: introduce GEN_VSX_HELPER_X1 macro to fpu_helper.c

Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_X1 macro which performs the decode based
upon xB at translation time.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 23d0766bd984c63bd600aaada1d7d534aed40f6d
      
https://github.com/qemu/qemu/commit/23d0766bd984c63bd600aaada1d7d534aed40f6d
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/translate/vsx-impl.inc.c

  Log Message:
  -----------
  target/ppc: introduce GEN_VSX_HELPER_R3 macro to fpu_helper.c

Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_R3 macro which performs the decode based
upon rD, rA and rB at translation time.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 99229620112a29b24f0ca5b7e16a2548d7318337
      
https://github.com/qemu/qemu/commit/99229620112a29b24f0ca5b7e16a2548d7318337
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/translate/vsx-impl.inc.c

  Log Message:
  -----------
  target/ppc: introduce GEN_VSX_HELPER_R2 macro to fpu_helper.c

Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_R2 macro which performs the decode based
upon rD and rB at translation time.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 6ae4a57ab037f921207d92568d18d1bd5f8b62de
      
https://github.com/qemu/qemu/commit/6ae4a57ab037f921207d92568d18d1bd5f8b62de
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/translate/vsx-impl.inc.c

  Log Message:
  -----------
  target/ppc: introduce GEN_VSX_HELPER_R2_AB macro to fpu_helper.c

Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_R2_AB macro which performs the decode based
upon rA and rB at translation time.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 2aba168e5044641111877fb1d65a0ddcf70ba298
      
https://github.com/qemu/qemu/commit/2aba168e5044641111877fb1d65a0ddcf70ba298
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/mem_helper.c
    M target/ppc/translate/vsx-impl.inc.c

  Log Message:
  -----------
  target/ppc: decode target register in VSX_VECTOR_LOAD_STORE_LENGTH at 
translation time

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 5ba5335d93cf235e5de065714ced2c1b0f4c9c6e
      
https://github.com/qemu/qemu/commit/5ba5335d93cf235e5de065714ced2c1b0f4c9c6e
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/int_helper.c
    M target/ppc/translate/vsx-impl.inc.c

  Log Message:
  -----------
  target/ppc: decode target register in VSX_EXTRACT_INSERT at translation time

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: c9f4e4d8b63259fdfba7b3a43a398c7acb90bf91
      
https://github.com/qemu/qemu/commit/c9f4e4d8b63259fdfba7b3a43a398c7acb90bf91
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/translate/vsx-impl.inc.c
    M target/ppc/translate/vsx-ops.inc.c

  Log Message:
  -----------
  target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro

Introduce a new GEN_VSX_HELPER_VSX_MADD macro for the generator function which
enables the source and destination registers to be decoded at translation time.

This enables the determination of a or m form to be made at translation time so
that a single helper function can now be used for both variants.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a2166410ad7434a6830288beb5858b22d5e35ec5
      
https://github.com/qemu/qemu/commit/a2166410ad7434a6830288beb5858b22d5e35ec5
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/ppc/spapr_pci.c
    M include/exec/memory.h
    M memory.c

  Log Message:
  -----------
  spapr_pci: Unregister listeners before destroying the IOMMU address space

Hot-unplugging a PHB with a VFIO device connected to it crashes QEMU:

-device spapr-pci-host-bridge,index=1,id=phb1 \
-device vfio-pci,host=0034:01:00.3,id=vfio0

(qemu) device_del phb1
[  357.207183] iommu: Removing device 0001:00:00.0 from group 1
[  360.375523] rpadlpar_io: slot PHB 1 removed
qemu-system-ppc64: memory.c:2742:
 do_address_space_destroy: Assertion `QTAILQ_EMPTY(&as->listeners)' failed.

'as' is the IOMMU address space, which indeed has a listener registered
to by vfio_connect_container() when the VFIO device is realized. This
listener is supposed to be unregistered by vfio_disconnect_container()
when the VFIO device is finalized. Unfortunately, the VFIO device hasn't
reached finalize yet at the time the PHB unrealize function is called,
and address_space_destroy() gets called with the VFIO listener still
being registered.

All regions have just been unmapped from the address space. Listeners
aren't needed anymore at this point. Remove them before destroying the
address space.

The VFIO code will try to remove them _again_ at device finalize,
but it is okay since memory_listener_unregister() is idempotent.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
[dwg: Correct spelling error pointed out by aik]
Signed-off-by: David Gibson <address@hidden>


  Commit: 981b1c6266c60f4eb86e09ef00f1b5dd046525c7
      
https://github.com/qemu/qemu/commit/981b1c6266c60f4eb86e09ef00f1b5dd046525c7
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/intc/spapr_xive.c
    M hw/intc/spapr_xive_kvm.c
    M hw/ppc/spapr_irq.c
    M include/hw/ppc/spapr_xive.h
    M include/hw/ppc/xive.h

  Log Message:
  -----------
  spapr/xive: rework the mapping the KVM memory regions

Today, the interrupt device is fully initialized at reset when the CAS
negotiation process has completed. Depending on the KVM capabilities,
the SpaprXive memory regions (ESB, TIMA) are initialized with a host
MMIO backend or a QEMU emulated backend. This results in a complex
initialization sequence partially done at realize and later at reset,
and some memory region leaks.

To simplify this sequence and to remove of the late initialization of
the emulated device which is required to be done only once, we
introduce new memory regions specific for KVM. These regions are
mapped as overlaps on top of the emulated device to make use of the
host MMIOs. Also provide proper cleanups of these regions when the
XIVE KVM device is destroyed to fix the leaks.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d0e9bc040771029b9ded7a0c303d1be714a9741e
      
https://github.com/qemu/qemu/commit/d0e9bc040771029b9ded7a0c303d1be714a9741e
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/ppc/spapr_irq.c
    M include/hw/ppc/spapr_irq.h

  Log Message:
  -----------
  spapr/xive: simplify spapr_irq_init_device() to remove the emulated init

The init_emu() handles are now empty. Remove them and rename
spapr_irq_init_device() to spapr_irq_init_kvm().

Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: fe9a9d527da8ae939ee7eb32cb0045d2c3f75a11
      
https://github.com/qemu/qemu/commit/fe9a9d527da8ae939ee7eb32cb0045d2c3f75a11
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/intc/xive.c

  Log Message:
  -----------
  ppc/xive: Force the Physical CAM line value to group mode

When an interrupt needs to be delivered, the XIVE interrupt controller
presenter scans the CAM lines of the thread interrupt contexts of the
HW threads of the chip to find a matching vCPU. The interrupt context
is composed of 4 different sets of registers: Physical, HV, OS and
User.

The encoding of the Physical CAM line depends on the mode in which the
interrupt controller is operating: CAM mode or block group mode.
Block group mode being the default configuration today on POWER9 and
the only one available on the next POWER10 generation, enforce this
encoding in the Physical CAM line :

    chip << 19 | 0000000 0 0001 thread (7Bit)

It fits the overall encoding of the NVT ids and simplifies the matching
algorithm in the presenter.

Fixes: d514c48d41fb ("ppc/xive: hardwire the Physical CAM line of the thread 
context")
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8256870ada9379abfd1f5b2c209ad01092dd0904
      
https://github.com/qemu/qemu/commit/8256870ada9379abfd1f5b2c209ad01092dd0904
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/intc/xive.c

  Log Message:
  -----------
  ppc/xive: Make the PIPR register readonly

When the hypervisor (KVM) dispatches a vCPU on a HW thread, it restores
its thread interrupt context. The Pending Interrupt Priority Register
(PIPR) is computed from the Interrupt Pending Buffer (IPB) and stores
should not be allowed to change its value.

Fixes: 207d9fe98510 ("ppc/xive: introduce the XIVE interrupt thread context")
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0df68c7ed6e030e69cf583d14ca90e536fadaa3c
      
https://github.com/qemu/qemu/commit/0df68c7ed6e030e69cf583d14ca90e536fadaa3c
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/intc/pnv_xive.c

  Log Message:
  -----------
  ppc/pnv: Rework cache watch model of PnvXIVE

When the software modifies the XIVE internal structures, ESB, EAS,
END, NVT, it also must update the caches of the different XIVE
sub-engines. HW offers a set of common interface for such purpose.

The CWATCH_SPEC register defines the block/index of the target and a
set of flags to perform a full update and to watch for update
conflicts.

The cache watch CWATCH_DATAX registers are then loaded with the target
data with a first read on CWATCH_DATA0. Writing back is done in the
opposit order, CWATCH_DATA0 triggering the update.

The SCRUB_TRIG registers are used to flush the cache in RAM, and to
possibly invalidate it. Cache disablement is also an option but as we
do not model the cache, these registers are no-ops

Today, the modeling of these registers is incorrect but it did not
impact the set up of a baremetal system. However, running KVM requires
a rework.

Fixes: 2dfa91a2aa5a ("ppc/pnv: add a XIVE interrupt controller model for 
POWER9")
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: aaa450300e82fb0f5cf31741a4fe6736acf3d6f5
      
https://github.com/qemu/qemu/commit/aaa450300e82fb0f5cf31741a4fe6736acf3d6f5
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/intc/xive.c

  Log Message:
  -----------
  ppc/xive: Fix TM_PULL_POOL_CTX special operation

When a CPU is reseted, the hypervisor (Linux or OPAL) invalidates the
POOL interrupt context of a CPU with this special command. It returns
the POOL CAM line value and resets the VP bit.

Fixes: 4836b45510aa ("ppc/xive: activate HV support")
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 1c3d4a8f4b4f24baa9dae31db0599925abc7d2a2
      
https://github.com/qemu/qemu/commit/1c3d4a8f4b4f24baa9dae31db0599925abc7d2a2
  Author: Greg Kurz <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M hw/intc/spapr_xive_kvm.c

  Log Message:
  -----------
  spapr/xive: Add proper rollback to kvmppc_xive_connect()

Make kvmppc_xive_disconnect() able to undo the changes of a partial
execution of kvmppc_xive_connect() and use it to perform rollback.

Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Message-Id: <156198735673.293938.7313195993600841641.stgit@bahia>
Signed-off-by: David Gibson <address@hidden>


  Commit: 506179e42112be77bfd071f050b15762d3b2cd43
      
https://github.com/qemu/qemu/commit/506179e42112be77bfd071f050b15762d3b2cd43
  Author: Peter Maydell <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M docs/specs/ppc-spapr-xive.rst
    M docs/specs/ppc-xive.rst
    M hw/intc/pnv_xive.c
    M hw/intc/spapr_xive.c
    M hw/intc/spapr_xive_kvm.c
    M hw/intc/xics.c
    M hw/intc/xics_kvm.c
    M hw/intc/xics_spapr.c
    M hw/intc/xive.c
    M hw/ppc/mac_newworld.c
    M hw/ppc/mac_oldworld.c
    M hw/ppc/pnv.c
    M hw/ppc/pnv_xscom.c
    M hw/ppc/ppc.c
    M hw/ppc/prep.c
    M hw/ppc/spapr_irq.c
    M hw/ppc/spapr_pci.c
    M include/exec/memory.h
    M include/hw/ppc/pnv.h
    M include/hw/ppc/pnv_xscom.h
    M include/hw/ppc/spapr.h
    M include/hw/ppc/spapr_irq.h
    M include/hw/ppc/spapr_xive.h
    M include/hw/ppc/xics.h
    M include/hw/ppc/xics_spapr.h
    M include/hw/ppc/xive.h
    M memory.c
    M pc-bios/spapr-rtas/Makefile
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/int_helper.c
    M target/ppc/internal.h
    M target/ppc/kvm.c
    M target/ppc/kvm_ppc.h
    M target/ppc/machine.c
    M target/ppc/mem_helper.c
    M target/ppc/translate/vsx-impl.inc.c
    M target/ppc/translate/vsx-ops.inc.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.1-20190702' into 
staging

ppc patch queue 2019-07-2

Here's my next pull request for qemu-4.1.  I'm not sure if this will
squeak in just before the soft freeze, or just after.  I don't think
it really matters - most of this is bugfixes anyway.  There's some
cleanups which aren't stictly bugfixes, but which I think are safe
enough improvements to go in the soft freeze.  There's no true feature
work.

Unfortunately, I wasn't able to complete a few of my standard battery
of pre-pull tests, due to some failures that appear to also be in
master.  I'm hoping that hasn't missed anything important in here.

Highlights are:
  * A number of fixe and cleanups for the XIVE implementation
  * Cleanups to the XICS interrupt controller to fit better with the new
    XIVE code
  * Numerous fixes and improvements to TCG handling of ppc vector
    instructions
  * Remove a number of unnnecessary #ifdef CONFIG_KVM guards
  * Fix some errors in the PCI hotplug paths
  * Assorted other fixes

# gpg: Signature made Tue 02 Jul 2019 07:07:15 BST
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>" [full]
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>" [full]
# gpg:                 aka "David Gibson (kernel.org) <address@hidden>" 
[unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-4.1-20190702: (49 commits)
  spapr/xive: Add proper rollback to kvmppc_xive_connect()
  ppc/xive: Fix TM_PULL_POOL_CTX special operation
  ppc/pnv: Rework cache watch model of PnvXIVE
  ppc/xive: Make the PIPR register readonly
  ppc/xive: Force the Physical CAM line value to group mode
  spapr/xive: simplify spapr_irq_init_device() to remove the emulated init
  spapr/xive: rework the mapping the KVM memory regions
  spapr_pci: Unregister listeners before destroying the IOMMU address space
  target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro
  target/ppc: decode target register in VSX_EXTRACT_INSERT at translation time
  target/ppc: decode target register in VSX_VECTOR_LOAD_STORE_LENGTH at 
translation time
  target/ppc: introduce GEN_VSX_HELPER_R2_AB macro to fpu_helper.c
  target/ppc: introduce GEN_VSX_HELPER_R2 macro to fpu_helper.c
  target/ppc: introduce GEN_VSX_HELPER_R3 macro to fpu_helper.c
  target/ppc: introduce GEN_VSX_HELPER_X1 macro to fpu_helper.c
  target/ppc: introduce GEN_VSX_HELPER_X2_AB macro to fpu_helper.c
  target/ppc: introduce GEN_VSX_HELPER_X2 macro to fpu_helper.c
  target/ppc: introduce separate generator and helper for xscvqpdp
  target/ppc: introduce GEN_VSX_HELPER_X3 macro to fpu_helper.c
  target/ppc: introduce separate VSX_CMP macro for xvcmp* instructions
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/efa85a4d1ab1...506179e42112